RADIO — 2.4 GHz radio

The 2.4 GHz radio transceiver is compatible with multiple radio standards such as 1 Mbps and 2 Mbps Bluetooth Low Energy modes, Long Range (125 kbps and 500 kbps) Bluetooth Low Energy modes, IEEE 802.15.4 250 kbps mode, as well as Nordic's proprietary 1 Mbps and 2 Mbps modes.

Listed here are main features for the RADIO:

Multidomain 2.4 GHz radio transceiver
- 1 Mbps and 2 Mbps Bluetooth Low Energy modes
- Long Range (125 kbps and 500 kbps) Bluetooth Low Energy modes
- Angle-of-arrival (AoA) and angle-of-departure (AoD) direction finding using Bluetooth Low Energy
- IEEE 802.15.4 250 kbps mode
- 1 Mbps and 2 Mbps Nordic proprietary modes
Best in class link budget and low power operation
Efficient data interface with EasyDMA support
Automatic address filtering and pattern matching

EasyDMA, in combination with an automated packet assembler, packet disassembler, automated CRC generator and CRC checker, makes it easy to configure and use the RADIO. See the following figure for details.

Figure 1. RADIO block diagram

The RADIO includes a device address match unit and an interframe spacing control unit that can be utilized to simplify address whitelisting and interframe spacing respectively in Bluetooth low energy and similar applications.

The RADIO also includes a received signal strength indicator (RSSI) and a bit counter. The bit counter generates events when a preconfigured number of bits are sent or received by the RADIO.

Packet configuration

A RADIO packet contains the fields PREAMBLE, ADDRESS, S0, LENGTH, S1, PAYLOAD, and CRC. For Long Range (125 kbps and 500 kbps) Bluetooth Low Energy modes, fields CI, TERM1, and TERM2 are also included.

The content of a RADIO packet is illustrated in the figures below. The RADIO sends the fields in the packet according to the order illustrated in the figures, starting on the left.

Figure 2. On-air packet layout

Figure 3. On-air packet layout for Long Range (125 kbps and 500 kbps) Bluetooth Low Energy modes

Not shown in the figures is the static payload add-on (the length of which is defined in PCNF1.STATLEN, and which is 0 bytes in a standard BLE packet). The static payload add-on is sent between PAYLOAD and CRC fields. The RADIO sends the different fields in the packet in the order they are illustrated above, from left to right.

PREAMBLE is sent with least significant bit first on air. The size of the PREAMBLE depends on the mode selected in the MODE register:

The PREAMBLE is one byte for MODE = Ble_1Mbit as well as all Nordic proprietary operating modes (MODE = Nrf_1Mbit and MODE = Nrf_2Mbit), and PCNF0.PLEN has to be set accordingly. If the first bit of the ADDRESS is 0, the preamble will be set to 0xAA. Otherwise the PREAMBLE will be set to 0x55.
For MODE = Ble_2Mbit, the PREAMBLE must be set to 2 bytes through PCNF0.PLEN. If the first bit of the ADDRESS is 0, the preamble will be set to 0xAAAA. Otherwise the PREAMBLE will be set to 0x5555.
For MODE = Ble_LR125Kbit and MODE = Ble_LR500Kbit, the PREAMBLE is 10 repetitions of 0x3C.
For MODE = Ieee802154_250Kbit, the PREAMBLE is 4 bytes and set to all zeros.

Radio packets are stored in memory inside instances of a RADIO packet data structure as illustrated below. The PREAMBLE, ADDRESS, CI, TERM1, TERM2, and CRC fields are omitted in this data structure. Fields S0, LENGTH, and S1 are optional.

Figure 4. Representation of a RADIO packet in RAM

The byte ordering on air is always least significant byte first for the ADDRESS and PAYLOAD fields, and most significant byte first for the CRC field. The ADDRESS fields are always transmitted and received least significant bit first. The CRC field is always transmitted and received most significant bit first. The endianness, i.e. the order in which the bits are sent and received, of the S0, LENGTH, S1, and PAYLOAD fields can be configured via PCNF1.ENDIAN.

The sizes of the S0, LENGTH, and S1 fields can be individually configured via S0LEN, LFLEN, and S1LEN in PCNF0 respectively. If any of these fields are configured to be less than 8 bits, the least significant bits of the fields are used.

If S0, LENGTH, or S1 are specified with zero length, their fields will be omitted in memory. Otherwise each field will be represented as a separate byte, regardless of the number of bits in their on-air counterpart.

Independent of the configuration of PCNF1.MAXLEN, the combined length of S0, LENGTH, S1, and PAYLOAD cannot exceed 258 bytes.

Address configuration

The on-air radio ADDRESS field is composed of two parts, the base address field and the address prefix field.

The size of the base address field is configurable via PCNF1.BALEN. The base address is truncated from the least significant byte if the PCNF1.BALEN is less than 4. See Definition of logical addresses.

The on-air addresses are defined in the BASE0/BASE1 and PREFIX0/PREFIX1 registers. It is only when writing these registers that the user must relate to the actual on-air addresses. For other radio address registers, such as the TXADDRESS, RXADDRESSES, and RXMATCH registers, logical radio addresses ranging from 0 to 7 are being used. The relationship between the on-air radio addresses and the logical addresses is described in the following table.

Table 1. Definition of logical addresses
Logical address	Base address	Prefix byte
0	BASE0	PREFIX0.AP0
1	BASE1	PREFIX0.AP1
2	BASE1	PREFIX0.AP2
3	BASE1	PREFIX0.AP3
4	BASE1	PREFIX1.AP4
5	BASE1	PREFIX1.AP5
6	BASE1	PREFIX1.AP6
7	BASE1	PREFIX1.AP7

Data whitening

The RADIO is able to do packet whitening and de-whitening, enabled in PCNF1.WHITEEN. When enabled, whitening and de-whitening will be handled by the RADIO automatically as packets are sent and received.

The whitening word is generated using polynomial g(D) = D⁷+ D⁴+ 1, which then is XORed with the data packet that is to be whitened, or de-whitened. The linear feedback shift register is initialized via DATAWHITEIV. See the following figure.

Figure 5. Data whitening and de-whitening

Whitening and de-whitening will be performed over the whole packet except for the preamble and the address fields.

CRC

The CRC generator in RADIO calculates the CRC over the whole packet excluding the preamble. If desirable, the address field can be excluded from the CRC calculation as well.

See CRCCNF register for more information.

The CRC polynomial is configurable as illustrated in the following figure, where bit 0 in the CRCPOLY register corresponds to X⁰ and bit 1 corresponds to X¹ etc. See CRCPOLY for more information.

Figure 6. CRC generation of an n bit CRC

The figure shows that the CRC is calculated by feeding the packet serially through the CRC generator. Before the packet is clocked through the CRC generator, the CRC generator's latches b₀ through b_n will be initialized with a predefined value specified in the CRCINIT register. After the whole packet has been clocked through the CRC generator, b₀ through b_n will hold the resulting CRC. This value will be used by the RADIO during both transmission and reception. Latches b₀ through b_n are not available to be read by the CPU at any time. However, a received CRC can be read by the CPU via the RXCRC register.

The length (n) of the CRC is configurable, see CRCCNF for more information.

Once the entire packet, including the CRC, has been received and no errors were detected, RADIO generates a CRCOK event. If CRC errors were detected, a CRCERROR event is generated.

The status of the CRC check can be read from the CRCSTATUS register after a packet has been received.

Radio states

Tasks and events are used to control the operating state of RADIO.

RADIO can enter the states described in the following table.

Table 2. RADIO state diagram
State	Description
DISABLED	No operations are going on inside the RADIO and the power consumption is at a minimum
RXRU	RADIO is ramping up and preparing for reception
RXIDLE	RADIO is ready for reception to start
RX	Reception has been started and the addresses enabled in the RXADDRESSES register are being monitored
TXRU	RADIO is ramping up and preparing for transmission
TXIDLE	RADIO is ready for transmission to start
TX	RADIO is transmitting a packet
RXDISABLE	RADIO is disabling the receiver
TXDISABLE	RADIO is disabling the transmitter

A state diagram showing an overview of RADIO is shown in the following figure.

Figure 7. Radio states

This figure shows how the tasks and events relate to the RADIO's operation. The RADIO does not prevent a task from being triggered from the wrong state. If a task is triggered from the wrong state, for example if the RXEN task is triggered from the RXDISABLE state, this may lead to incorrect behavior. The PAYLOAD event is always generated even if the payload is zero.

The END to START shortcut should not be used with IEEE 802.15.4 250 kbps mode. Use the PHYEND to START shortcut instead.

The END to START shortcut should not be used with Long Range (125 kbps and 500 kbps) Bluetooth Low Energy modes. Use the PHYEND to START shortcut instead.

Transmit sequence

Before the RADIO is able to transmit a packet, it must first ramp-up in TX mode. See TXRU in Radio states and Transmit sequence. A TXRU ramp-up sequence is initiated when the TXEN task is triggered. After the RADIO has successfully ramped up it will generate the READY event indicating that a packet transmission can be initiated. A packet transmission is initiated by triggering the START task. The START task can first be triggered after the RADIO has entered into the TXIDLE state.

The following figure illustrates a single packet transmission where the CPU manually triggers the different tasks needed to control the flow of the RADIO, i.e. no shortcuts are used. If shortcuts are not used, a certain amount of delay caused by CPU execution is expected between READY and START, and between END and DISABLE. As illustrated in Transmit sequence the RADIO will by default transmit 1s between READY and START, and between END and DISABLED. What is transmitted can be programmed through the DTX field in the MODECNF0 register.

Figure 8. Transmit sequence

The following figure shows a slightly modified version of the transmit sequence where RADIO is configured to use shortcuts between READY and START, and between END and DISABLE, which means that no delay is introduced.

Figure 9. Transmit sequence using shortcuts to avoid delays

RADIO is able to send multiple packets one after the other without having to disable and re-enable the RADIO between packets, as illustrated in the following figure.

Figure 10. Transmission of multiple packets

Receive sequence

Before RADIO is able to receive a packet, it must first ramp up in RX mode. See RXRU in Radio states and Receive sequence for more information.

An RXRU ramp up sequence is initiated when the RXEN task is triggered. After RADIO has successfully ramped up it will generate the READY event indicating that a packet reception can be initiated. A packet reception is initiated by triggering the START task. As illustrated in Radio states, the START task can first be triggered after RADIO has entered into the RXIDLE state.

The following figure shows a single packet reception where the CPU manually triggers the different tasks needed to control the flow of RADIO, i.e. no shortcuts are used. If shortcuts are not used, a certain amount of delay caused by CPU execution is expected between READY and START, and between END and DISABLE. RADIO will be listening and possibly receiving undefined data, represented with an 'X', from START and until a packet with valid preamble (P) is received.

Figure 11. Receive sequence

The following figure shows a modified version of the receive sequence, where RADIO is configured to use shortcuts between READY and START, and between END and DISABLE, which means that no delay is introduced.

Figure 12. Receive sequence using shortcuts to avoid delays

RADIO is able to receive consecutive packets without having to disable and re-enable RADIO between packets, as illustrated in the following figure.

Figure 13. Reception of multiple packets

Received signal strength indicator (RSSI)

RADIO implements a mechanism for measuring the power in the received signal. This feature is called received signal strength indicator (RSSI).

The RSSI is measured continuously and the value filtered using a single-pole IIR filter. After a signal level change, the RSSI will settle after approximately RSSI_SETTLE.

Sampling of the received signal strength is started by using the RSSISTART task. The sample can be read from the RSSISAMPLE register.

The sample period of the RSSI is defined by RSSI_PERIOD. The RSSISAMPLE will hold the filtered received signal strength after this sample period.

For the RSSI sample to be valid, the RADIO has to be enabled in receive mode (RXEN task) and the reception has to be started (READY event followed by START task).

Interframe spacing (IFS)

Interframe spacing (IFS) is defined as the time, in microseconds, between two consecutive packets, starting from when the end of the last bit of the previous packet is received, to the beginning of the first bit of the subsequent packet that is transmitted. The RADIO is able to enforce this interval, as specified in the TIFS register, as long as the TIFS is not specified to be shorter than the RADIO's turnaround time, i.e. the time needed to switch off the receiver, and then switch the transmitter back on. The TIFS register can be written any time before the last bit on air is received.

This timing is illustrated in the figure below.

Figure 14. IFS timing detail

The TIFS duration starts after the last bit on air (just before the END event), and elapses with first bit being transmitted on air (just after READY event).

TIFS is only enforced if the shortcuts END to DISABLE and DISABLED to TXEN or END to DISABLE and DISABLED to RXEN are enabled.

TIFS is qualified for use in IEEE 802.15.4 250kbps mode, Long Range (125 kbps and 500 kbps) Bluetooth Low Energy modes, and 1 Mbps and 2 Mbps Bluetooth Low Energy modes, using the default ramp-up mode.

SHORTS and TIFS registers are not double-buffered, and can be updated at any point before the last bit on air is received. The MODE register is double-buffered and sampled at the TXEN or RXEN task.

Device address match

The device address match feature is tailored for address whitelisting in Bluetooth low energy and similar implementations.

This feature enables on-the-fly device address matching while receiving a packet on air. This feature only works in receive mode and when the RADIO is configured for little endian, see PCNF1.ENDIAN.

The device address match unit assumes that the first 48 bits of the payload are the device address and that bit number 6 in S0 is the TxAdd bit. See the Bluetooth® Core Specification for more information about device addresses, TxAdd, and whitelisting.

The RADIO is able to listen for eight different device addresses at the same time. These addresses are specified in a DAB/DAP register pair, one pair per address, in addition to a TxAdd bit configured in the DACNF register. The DAB register specifies the 32 least significant bits of the device address, while the DAP register specifies the 16 most significant bits of the device address.

Each of the device addresses can be individually included or excluded from the matching mechanism. This is configured in the DACNF register.

Bit counter

The RADIO implements a simple counter that can be configured to generate an event after a specific number of bits have been transmitted or received.

By using shortcuts, this counter can be started from different events generated by the RADIO and count relative to these.

The bit counter is started by triggering the BCSTART task, and stopped by triggering the BCSTOP task. A BCMATCH event will be generated when the bit counter has counted the number of bits specified in the BCC register. The bit counter will continue to count bits until the DISABLED event is generated or until the BCSTOP task is triggered. After a BCMATCH event, the CPU can reconfigure the BCC value for new BCMATCH events within the same packet.

The bit counter can only be started after the RADIO has received the ADDRESS event.

The bit counter will stop and reset on either the BCSTOP, STOP, or DISABLE task, or the END event.

The following figure shows how the bit counter can be used to generate a BCMATCH event in the beginning of the packet payload, and again generate a second BCMATCH event after sending 2 bytes (16 bits) of the payload.

Figure 15. Bit counter example

RADIO bit counter example: combined length of S0, L and S1 is 12 bits

Direction finding

The RADIO implements the Angle-of-Arrival (AoA) and Angle-of-Departure (AoD) Bluetooth Low Energy feature, which can be used to determine the direction of a peer device. The feature is available for the BLE 1 Mbps and BLE 2 Mbps modes.

When using this feature, the transmitter sends a packet with a continuous tone extension (CTE) appended to the packet, after the CRC. During the CTE, the receiver can take IQ samples of the incoming signal.

An antenna array is employed at the transmitter (AoD) or at the receiver (AoA). The AoD transmitter, or AoA receiver, switches between the antennas, in order to collect IQ samples from the different antenna pairs. The IQ samples can be used to calculate the relative path lengths between the antenna pairs, which can be used to estimate the direction of the transmitter.

CTE format

The CTE is from 16 µs to 160 µs and consists of an unwhitened sequence of 1's, equivalent to a continuous tone nominally offset from the carrier by +250 kHz for the 1 Mbps PHY and +500 kHz for the 2 Mbps BLE PHYs. The format of the CTE, when switching and/or sampling, is shown in the following figure.

Figure 16. Constant tone extension (CTE) structure

Antenna switching is performed during switch slots and the guard period. The AoA/AoD feature requires that one IQ sample is taken for each microsecond within the reference period, and once for each sample slot. Oversampling is possible by changing the sample spacing as described in IQ sampling. The switch slot and sample slot durations are either 1 or 2 µs, but must be equal. The format of the CTE and switching and sampling procedures may be configured prior to, or during, packet transmission and reception. Alternatively, during packet reception, these operations can be configured by reading specific fields of the packet contents.

Mode

Depending on the DFEMODE, the device performs the procedures shown in the following table.

Table 3. AoA/AoD Procedures performed as a function of DFEMODE and TX/RX mode
		DFEMODE
		AOA		AOD
		TX	RX	TX	RX
AoA/AoD Procedure	Generating and transmitting CTE	x		x
	Receiving, interpreting, and sampling CTE		x		x
	Antenna switching		x	x

Inline configuration

When inline configuration is enabled during RX, further configuration of the AoA/AoD procedures is performed based on the values of the CP bit and the CTEInfo octet within the packet. This is enabled by setting CTEINLINECONF.CTEINLINECTRLEN. The CTEInfo octet is present only if the CP bit is set. The position of the CP bit and CTEInfo octet depends on whether the packet has a Data Channel PDU (CTEINLINECONF.CTEINFOINS1=InS1), or an Advertising Channel PDU (CTEINLINECONF.CTEINFOINS1=NotInS1).

Data channel PDU

For Data Channel PDUs, PCNF0.S0LEN must be 1 byte, and PCNF0.LFLEN must be 8 bits. To determine if S1 is present, the registers CTEINLINECONF.S0MASK and CTEINLINECONF.S0CONF forms a bitwise mask-and-test for the S0 field. If the bitwise AND between S0 and S0MASK equals S0CONF, then S1 is determined to be present. When present, the value of PCNF0.S1LEN will be ignored, as this is decided by the CP bit in the the following figure.

Figure 17. Data channel PDU header

When encrypting and decrypting BLE packets using the CCM peripheral, it is also required to set PCNF0.S1INCL=1. The CCM mode must be configured to use an 8-bit length field. The value of the CP bit is included in the calculation of the MIC, while the S1 field is ignored by the CCM calculation.

Advertising channel PDU

For advertising channel PDUs, the CTEInfo Flag replaces the CP bit. The CTEInfo Flag is within the extended header flag field in some of the advertising PDUs that employ the common extended advertising payload format (i.e. AUX_SYNC_IND, AUX_CHAIN_IND). The format of such packets is shown in the following figure.

Figure 18. Advertising channel PDU header

The CTEINLINECONF.S0CONF and CTEINLINECONF.S0MASK fields can be configured to accept only certain advertising PDU Types. If the extended header length is non-zero, the CTEInfo extended header flag is checked to determine whether CTEInfo is present. If a bit before the CTEInfo flag within the extended header flags is set, then the CTEInfo position is postponed 6 octets.

CTEInfo parsing

The CTEInfo field is shown in the following figure.

Figure 19. CTEInfo field

The CTETIME field defines the length of the CTE in 8 µs units. The valid upper bound of values can be adjusted using CTEINLINECONF.CTETIMEVALIDRANGE, including allowing use of the RFU bit within this field. If the CTETIME field is an invalid value of either 0 or 1, the CTE is assumed to be the minimum valid length of 16 µs. The slot duration is determined by the CTEType field. In RX this determines whether the sample spacing as defined in CTEINLINECONF.CTEINLINERXMODE1US or CTEINLINECONF.CTEINLINERXMODE2US is used.

Table 4. Switching and sampling spacing based on CTEType
CTEType	Description	TX switch spacing	RX sample spacing during reference period	Sample spacing RX during reference period
0	AoA, no switching	-	TSAMPLESPACING1	TSAMPLESPACING2
1	AoD, 1 µs slots	2 µs	TSAMPLESPACING1	CTEINLINERXMODE1US
2	AoD, 2 µs slots	4 µs	TSAMPLESPACING1	CTEINLINERXMODE2US
3	Reserved for future use

Manual configuration

If CTEINLINECONF.CTEINLINECTRLEN is not set, then the packet is not parsed to determine the CTE parameters, and the antenna switching and sampling is controlled by other registers, see Antenna switching. The length of the CTE is given in 8 µs units by DFECTRL1.NUMBEROF8US. The start of the antenna switching and/or sampling (denoted as an AoA/AoD procedure), can be configured to start at some trigger with an additional offset. Using DFECTRL1.DFEINEXTENSION, the trigger can be configured to be the end of the CRC, or alternatively, the ADDRESS event. The additional offset for antenna switching is configured using DFECTRL2.TSWITCHOFFSET. Similarly, the additional offset for antenna sampling is configured using DFECTRL2.TSAMPLEOFFSET.

Receive- and transmit sequences

The addition of the CTE to the transmitted packet is illustrated in the following figure.

Figure 20. Transmit sequence with DFE

The prescence of CTE within a received packet is signalled by the CTEPRESENT event illustrated in the figure below.

Figure 21. Receive sequence with DFE

Antenna switching

The RADIO can control up to 8 GPIO pins in order to control external antenna switches used in direction finding.

Pin configuration

The eight antenna selection signals are mapped to physical pins according to the pin numbers specified in the PSEL.DFEGPIO[n] registers. Only pins that have the PSEL.DFEGPIO[n].CONNECTED field set to Connected will be controlled by the RADIO. Pins that are Disconnected will be controlled by GPIO.

During transmission in AoD TX mode or reception in AoA RX mode, the RADIO automatically acquires the pins as needed. At times when the RADIO does not use the pin, the pin is released to its default state and controlled by the GPIO configuration. Thus, the pin must be configured using the GPIO peripheral.

Table 5. Pin configuration matrix for a connected and enabled pin [n]
Pin acquired by RADIO	Direction	Value	Comment
Yes	Output	Specified in SWITCHPATTERN	Pin acquired by RADIO, and in use for DFE.
No	Specified by GPIO	Specified by GPIO	DFE not in progress. Pin has not been acquired by RADIO, but is available for DFE use.

Switch pattern configuration

The values of the GPIOs while switching during the CTE are configured by writing successively to the SWITCHPATTERN register. The first write to SWITCHPATTERN is the GPIO pattern applied from the call of TASKS_TXEN or TASKS_RXEN until the first antenna switch is triggered. The second write sets the pattern for the reference period and is applied at the start of the guard period. The following writes set the pattern for the remaining switch slots and are applied at the start of each switch slot. If writing beyond the total number of antenna slots, the pattern will wrap to SWITCHPATTERN[2] and start over again. During operation, when the end of the SWITCHPATTERN buffer is reached, the RADIO cycles back to SWITCHPATTERN[2]. At the end of the AoA/AoD procedure, SWITCHPATTERN[0] is applied to DFECTRL1.TSWITCHSPACING after the previous antenna switch. The SWITCHPATTERN buffer can be erased/cleared using CLEARPATTERN.

A minimum number of three patterns must be written to the SWITCHPATTERN register.

If CTEINLINECONF.CTEINLINECTRLEN is not set, then the antenna switch spacing is determined by DFECTRL1.TSWITCHSPACING (otherwise described by Switching and sampling spacing based on CTEType). DFECTRL2.TSWITCHOFFSET determines the position of the first switch compared to the configurable start of CTE (see DFECTRL1.DFEINEXTENSION).

IQ sampling

The RADIO uses DMA to write IQ samples recorded during the CTE to RAM. Alternatively, the magnitude and phase of the samples can be recorded using the DFECTRL1.SAMPLETYPE field. The samples are written to the location in RAM specified by DFEPACKET.PTR. The maximum number of samples to transfer are specified by DFEPACKET.MAXCNT and the number of samples transferred are given in DFEPACKET.AMOUNT. The IQ samples are recorded with respect to the RX carrier frequency. The format of the samples is provided in the following table.

Table 6. Format of samples
SAMPLETYPE	Field	Bits	Description
0: I_Q (default)	Q	31:16	12 bits signed, sign extended to 16 bits. Out of range samples are saturated at value -32768.
0: I_Q (default)	I	15:0
1: MagPhase	reserved	31:29	Always zero
	magnitude	28:16	13 bits unsigned. Equals 1.646756*sqrt(I^2+Q^2).
	phase	15:0	9 bits signed, sign extended to 16 bits. Equals 64*atan2(Q, I) in the range [-201,201].

Oversampling is configured separately for the reference period and for the time after the reference period. During the reference period, the sample spacing is determined by DFECTRL1.TSAMPLESPACINGREF. DFECTRL2.TSAMPLEOFFSET determines the position of the first sample relative to the end of the last bit of the CRC.

For the time after the reference period, if CTEINLINECONF.CTEINLINECTRLEN is disabled, the sample spacing is set in DFECTRL1.TSAMPLESPACING. However, when CTEINLINECONF.CTEINLINECTRLEN is enabled, the sample spacing is determined by two different registers, depending on whether the device is in AoA or AoD RX-mode.

For AoD RX mode, the sample spacing after the reference period is determined by the CTEType in the packet, as listed in the following table.

Table 7. Sample spacing when CTEINLINECONF.CTEINLINECTRLEN is set and the device is in AoD RX mode
CTEType	Sample spacing
AoD 1 µs slots	CTEINLINECONF.CTEINLINERXMODE1US
AoD 2 µs slots	CTEINLINECONF.CTEINLINERXMODE2US
Other	DFECTRL1.TSAMPLESPACING

For AoA RX mode, the sample spacing after the reference period is determined by DFECTRL1.TSWITCHSPACING, as listed in the following table.

Table 8. Sample spacing when CTEINLINECONF.CTEINLINECTRLEN is set and the device is in AoA RX mode
DFECTRL1.TSWITCHSPACING	Sample spacing
2 µs	CTEINLINECONF.CTEINLINERXMODE1US
4 µs	CTEINLINECONF.CTEINLINERXMODE2US
Other	DFECTRL1.TSAMPLESPACING

For the reference and switching periods, DFECTRL1.TSAMPLESPACINGREF and DFECTRL1.TSAMPLESPACING can be used to achieve oversampling.

IEEE 802.15.4 operation

With the MODE=Ieee802154_250kbit the RADIO will comply with the IEEE 802.15.4-2006 standard implementing its 250 kbps, 2450 MHz, O-QPSK PHY.

The IEEE 802.15.4 standard differs from Nordic's proprietary and Bluetooth low energy modes. Notable differences include modulation scheme, channel structure, packet structure, security, and medium access control.

The main features of the IEEE 802.15.4 mode are:

Ultra-low power 250 kbps, 2450 MHz, IEEE 802.15.4-2006 compliant link
Clear channel assessment
Energy detection scan
CRC generation

Packet structure

The IEEE 802.15.4 standard defines an on-the-air frame/packet that is different from what is used in BLE mode.

The following figure provides an overview of the physical frame structure and its timing.

Figure 22. IEEE 802.15.4 frame format (PPDU)

The standard uses the term octet for an 8-bit storage unit within the PPDU. For timing, the value symbol is used, and it has a duration of 16 µs.

The total usable payload (PSDU) is 127 octets, but when CRC is in use, this is reduced to 125 octets of usable payload.

The preamble sequence consists of four octets that are all zero, and are used for synchronizing the RADIO's receiver. Following the preamble is the single octet start of frame delimiter (SFD), with a fixed value of 0xA7. An alternate SFD can be programmed through the SFD register, providing an initial level of frame filtering for those who choose non-standard compliance. It is a valuable feature when operating in a congested or private network. The preamble sequence and the SFD are generated by the RADIO, and are not programmed by the user into the frame buffer.

Following the five octet synchronization header (SHR) is the single octet phy header (PHR). The least significant seven bits of PHR denote the frame length of the following PSDU. The most significant bit is reserved and is set to zero for frames that are standard compliant. The RADIO reports all eight bits which can be used to carry additional information. The PHR is the first byte written to the frame data memory pointed to by PACKETPTR. Frames with zero length are discarded, and the FRAMESTART event is not generated in this case.

The next N octets carry the data of the PHY packet, where N equals the value of the PHR. For an implementation also using the IEEE 802.15.4 MAC layer, the PHY data is a MAC frame of N-2 octets, since two octets occupy a CRC field.

An IEEE 802.15.4 MAC layer frame consists of the following:

A header:
- The frame control field (FCF)
- The sequence number
- Addressing fields
A payload
The 16-bit frame control sequence (FCS)

Figure 23. IEEE 802.15.4 frame format (MPDU)

The two FCF octets contain information about the frame type, addressing, and other control flags. This field is decoded when using the assisted operating modes offered by the RADIO.

The sequence number is a single octet in size and is unique for a frame. It is used in the associated acknowledgement frame sent upon successful frame reception.

The addressing field can be zero (acknowledgement frame) or up to 20 octets in size. The field is used to direct packets to the correct recipient and denote its origin. IEEE 802.15.4 bases its addressing on networks being organized in PANs with 16-bit identifier and nodes having a 16-bit or 64-bit address. In the assisted receive mode, these parameters are analyzed for address matching and acknowledgement.

The MAC payload carries the data of the next higher layer, or in the case of a MAC command frame, information used by the MAC layer itself.

The two last octets contain the 16-bit ITU-T CRC. The FCS is calculated over the MAC header (MHR) and MAC payload (MSDU) parts of the frame. This field is calculated automatically when sending a frame, or indicated in the CRCSTATUS register when a frame is received. If configured, this feature is taken care of autonomously by the CRC module.

Operating frequencies

The IEEE 802.15.4 standard defines 16 channels, 11 - 26, of 5 MHz each, in the 2450 MHz frequency band.

To choose the correct channel center frequency, the FREQUENCY register must be programmed according to the table below.

Table 9. IEEE 802.15.4 center frequency definition
IEEE 802.15.4 channel	Center frequency (MHz)	FREQUENCY setting
Channel 11	2405	5
Channel 12	2410	10
Channel 13	2415	15
Channel 14	2420	20
Channel 15	2425	25
Channel 16	2430	30
Channel 17	2435	35
Channel 18	2440	40
Channel 19	2445	45
Channel 20	2450	50
Channel 21	2455	55
Channel 22	2460	60
Channel 23	2465	65
Channel 24	2470	70
Channel 25	2475	75
Channel 26	2480	80

Energy detection (ED)

As required by the IEEE 802.15.4 standard, it must be possible to sample the received signal power within the bandwidth of a channel, for the purpose of determining presence of activity.

To prevent the channel signal from being decoded, the shortcut between the READY event and the START task should be disabled before putting the RADIO in receive mode. The energy detection (ED) measurement time, where RSSI samples are averaged, is 8 symbol periods, corresponding to 128 µs. The standard further specifies the measurement to be a number between 0 and 255, where 0 shall indicate received power less than 10 dB above the selected receiver sensitivity. The power range of the ED values must be at least a 40 dB linear mapping with accuracy of ±6 dB. See section 6.9.7 Receiver ED in the IEEE 802.15.4 standard for further details.

The following example shows how to perform a single energy detection measurement and convert to IEEE 802.15.4 scale.

IEEE 802.15.4 ED measurement example

#define ED_RSSISCALE 4 // From electrical specifications
uint8_t sample_ed(void)
{
    int val;
    NRF_RADIO->TASKS_EDSTART = 1; // Start
    while (NRF_RADIO->EVENTS_EDEND != 1) {
        // CPU can sleep here or do something else
        // Use of interrupts are encouraged
        }
    val = NRF_RADIO->EDSAMPLE * ED_RSSISCALE; // Read level
    return (uint8_t)(val>255 ? 255 : val);    // Convert to IEEE 802.15.4 scale
}

For scaling between hardware value and dBm, see equation Conversion between hardware value and dBm.

The mlme-scan.req primitive of the MAC layer uses the ED measurement to detect channels where there might be wireless activity. To assist this primitive, a tailored mode of operation is available where the ED measurement runs for a defined number of iterations keeping track of the maximum ED level. This is enganged by writing the EDCNT register to a value different from 0, where it will run the specified number of iterations and report the maximum energy measurement in the EDSAMPLE register. The scan is started with EDSTART task and its end indicated with the EDEND event. This significantly reduces the interrupt frequency and therefore power consumption. The following figure shows how the ED measurement will operate depending on the EDCNT register.

Figure 24. Energy detection measurement examples

The scan is stopped by writing the EDSTOP task. It will be followed by the EDSTOPPED event when the module has terminated.

Clear channel assessment (CCA)

IEEE 802.15.4 implements a listen-before-talk channel access method to avoid collisions when transmitting, known as carrier sense multiple access with collision avoidance (CSMA-CA). The key part of this is measuring if the wireless medium is busy or not.

The following clear channel assesment modes are supported:

CCA Mode 1 (energy above threshold) - The medium is reported busy upon detecting any energy above the ED threshold.
CCA Mode 2 (carrier sense only) - The medium is reported busy upon detection of a signal compliant with the IEEE 802.15.4 standard with the same modulation and spreading characteristics.
CCA Mode 3 (carrier sense with energy above threshold) - The medium is reported busy using a logical combination (AND/OR) between the results from CCA Mode 1 and CCA Mode 2.

The clear channel assessment should survey a period equal to 8 symbols or 128 µs.

The RADIO must be in receive mode and be able to receive correct packets when performing the CCA. The shortcut between READY and START must be disabled if baseband processing is not to be performed while the measurement is running.

CCA Mode 1

CCA Mode 1 is enabled by first configuring the field CCACTRL.CCAMODE=EdMode and writing the CCACTRL.CCAEDTHRES field to a chosen value. Once the CCASTART task is written, the RADIO will perform a ED measurement for 8 symbols and compare the measured level with that found in the CCACTRL.CCAEDTHRES field. If the measured value is higher than or equal to this threshold, the CCABUSY event is generated. If the measured level is less than the threshold, the CCAIDLE event is generated.

CCA Mode 2

CCA Mode 2 is enabled by configuring CCACTRL.CCAMODE=CarrierMode. The RADIO will sample to see if a valid SFD is found during the 8 symbols. If a valid SFD is detected, the CCABUSY event is generated and the device should not send any data. The CCABUSY event is also generated if the scan was performed during an ongoing frame reception. In the case where the measurement period completes with no SFD detection, the CCAIDLE event is generated. When CCACTRL.CCACORRCNT is not zero, the algorithm will look at the correlator output in addition to the SFD detection signal. If a SFD is reported during the scan period, it will terminate immidiately indicating busy medium. Similarly, if the number of peaks above CCACTRL.CCACORRTHRES crosses the CCACTRL.CCACORRCNT, the CCACTRL.CCABUSY event is generated. If less than CCACORRCOUNT crossings are found and no SFD is reported, the CCAIDLE event will be generated and the device can send data.

CCA Mode 3

CCA Mode 3 is enabled by configuring CCACTRL.CCAMODE=CarrierAndEdMode or CCACTRL.CCAMODE=CarrierOrEdMode, performing the required logical combination of the result from CCA Mode 1 and 2. The CCABUSY or CCAIDLE events are generated by ANDing or ORing the energy above threshold and carrier detection scans.

Shortcuts

An ongoing CCA can always be stopped by issuing the CCASTOP task. This will trigger the associated CCASTOPPED event.

For CCA mode automation, a number of shortcuts are available.

To automatically switch between RX (when performing the CCA) and to TX where the packet is sent, the shortcut between CCAIDLE and TXEN, in conjunction with the short between CCAIDLE and STOP muse be used.
To automatically disable the RADIO whenever the CCA reports a busy medium, the shortcut between CCABUSY and DISABLE can be used.
To immediately start a CCA after ramping up into RX mode, the shortcut between RXREADY and CCASTART can be used.

Conversion

The conversion from a CCAEDTHRES, LQI, or EDSAMPLE value to dBm can be done with the following equation, where VAL_HARDWARE is either CCAEDTHRES, LQI, or EDSAMPLE. LQI and EDSAMPLE are hardware-reported values, while CCAEDTHRES is set by software. Constants ED_RSSISCALE and ED_RSSIOFFS are from electrical specifications.

Figure 25. Conversion between hardware value and dBm

P_RF[dBm] = ED_RSSIOFFS + VAL_HARDWARE

The ED_RSSISCALE constant is used to calculate power in 802.15.4 units (0-255):

Figure 26. Conversion between hardware value and 802.15.4 units (0-255)

P_RF[802.15.4 units] = MIN( ED_RSSISCALE x VAL_HARDWARE, 255 )

Cyclic redundancy check (CRC)

IEEE 802.15.4 uses a 16-bit ITU-T cyclic redundancy check (CRC) calculated over the MAC header (MHR) and MAC service data unit (MSDU).

The standard defines the following generator polynomial:

G(x) = x¹⁶ + x¹² + x⁵ + 1

In receive mode the RADIO will trigger the CRC module when the first octet after the frame length (PHR) is received. The CRC will then update on each consecutive octet received. When a complete frame is received the CRCSTATUS register will be updated accordingly and the CRCOK or CRCERROR events generated. When the CRC module is enabled it will not write the two last octets (CRC) to the frame Data RAM. When transmitting, the CRC will be computed on the fly, starting with the first octet after PHR, and inserted as the two last octets in the frame. The EasyDMA will fetch frame length minus 2 octets from RAM and insert the CRC octets insitu.

The following code shows how to configure the CRC module for correct operation when in IEEE 802.15.4 mode. The CRCCNF is written to 16-bit CRC and the CRCPOLY is written to 0x11021. The start value used by IEEE 802.15.4 is zero and CRCINIT is configured to reflect this.

/* 16-bit CRC with ITU-T polynomial with 0 as start condition*/
NRF_RADIO->CRCCNF = ((RADIO_CRCCNF_SKIPADDR_Ieee802154 << RADIO_CRCCNF_SKIPADDR_Pos) |
                    (RADIO_CRCCNF_LEN_Two << RADIO_CRCCNF_LEN_Pos));
NRF_RADIO->CRCPOLY = 0x11021;
NRF_RADIO->CRCINIT = 0;

The ENDIANESS subregister must be set to little-endian since the FCS field is transmitted from left bit to right.

Transmit sequence

The transmission is started by first putting the RADIO in receive mode and triggering the RXEN task.

An outline of the IEEE 802.15.4 transmission is illustrated in the following figure.

Figure 27. IEEE 802.15.4 transmit sequence

The receiver will ramp up and enter the RXIDLE state where the READY event is generated. Upon receiving the ready event, the CCA is started by triggering the CCASTART task. The chosen mode of assessment (CCACTRL.CCAMODE register) will be performed and signal the CCAIDLE or CCABUSY event 128 µs later. If the CCABUSY event is received, the RADIO will have to retry the CCA after a specific back-off period. This is outlined in the IEEE 802.15.4 standard, Figure 69 in section 7.5.1.4 The CSMA-CA algorithm.

If the CCAIDLE event is generated, a write to the TXEN task register enters the RADIO in TXRU state. The READY event will be generated when the RADIO is in TXIDLE state and ready to transmit. With the PACKETPTR pointing to the length (PHR) field of the frame, the START task can be written. The RADIO will send the four octet preamble sequence followed by the start of frame delimiter (SFD register). The first byte read from the Data RAM is the length field (PHR) followed by the transmission of the number of bytes indicated as the frame length. If the CRC module is configured it will run for PHR-2 octets. The last two octets will be substituted with the results from running the CRC. The necessary CRC parameters are sampled on the START task. The FCS field of the frame is little endian.

In addition to the already available shortcuts, one is provided between READY event and CCASTART task so that a CCA can automatically start when the receiver is ready. A second shortcut has been added between CCAIDLE event and the TXEN task, so that upon detecting a clear channel the RADIO can immediately enter transmit mode.

Receive sequence

The reception is started by first putting the RADIO in receive mode. After writing to the RXEN task, the RADIO will start ramping up and enter the RXRU state.

When the READY event is generated, the RADIO enters the RXIDLE mode. For the baseband processing to be enabled, the START task must be written. An outline of the IEEE 802.15.4 reception can be found in the following figure.

Figure 28. IEEE 802.15.4 receive sequence

When a valid SHR is received, the RADIO will start storing future octets (starting with PHR) to the data memory pointed to by PACKETPTR. After the SFD octet is received, the FRAMESTART event is generated. If the CRC module is enabled it will start updating with the second byte received (first byte in payload) and run for the full frame length. The two last bytes in the frame are not written to RAM when CRC is configured. However, if the result of the CRC after running the full frame is zero, the CRCOK event will be generated. The END event is generated when the last octet has been received and is available in data memory.

When a packet is received, a link quality indicator (LQI) is also generated and appended immediately after the last received octet. When using an IEEE 802.15.4 compliant frame, this will be just after the MSDU since the FCS is not reported. In the case of a non-compliant frame, it will be appended after the full frame. The LQI reported by hardware must be converted to IEEE 802.15.4 range by an 8-bit saturating multiplication of 4, as shown in IEEE 802.15.4 ED measurement example. The LQI is only valid for frames equal to or longer than three octets. When receiving a frame, the RSSI (reported as negative dB) will be measured at three points during the reception. These three values will be sorted and the middle one selected (median 3) to be remapped within the LQI range. The following figure illustrates the LQI measurement and how the data is arranged in data memory.

Figure 29. IEEE 802.15.4 frame in data memory

A shortcut has been added between the FRAMESTART event and the BCSTART task. This can be used to trigger a BCMATCH event after N bits, such as when inspecting the MAC addressing fields.

Interframe spacing (IFS)

The IEEE 802.15.4 standard defines a specific time that is alotted for the MAC sublayer to process received data. Interframe spacing (IFS) is used to prevent two frames from being transmitted too close together. If the transmission is requesting an acknowledgement, the space before the second frame shall be at least one IFS period.

The IFS is determined to be one of the following:

IFS equals macMinSIFSPeriod (12 symbols) if the MPDU is less than or equal to aMaxSIFSFrameSize (18 octets) octets
IFS equals macMinLIFSPeriod (40 symbols) if the MPDU is larger than aMaxSIFSFrameSize

Using the efficient assisted modes in the RADIO, the TIFS will be programmed with the correct value based on the frame being transmitted. If the assisted modes are not in use, the TIFS register must be updated manually. The following figure provides details on what IFS period is valid in both acknowledged and unacknowledged transmissions.

Figure 30. Interframe spacing examples

EasyDMA

The RADIO uses EasyDMA to read and write packets to RAM without CPU involvement.

As illustrated in RADIO block diagram, the RADIO's EasyDMA utilizes the same PACKETPTR for receiving and transmitting packets. This pointer should be reconfigured by the CPU each time before RADIO is started by the START task. The PACKETPTR register is double-buffered, meaning that it can be updated and prepared for the next transmission.

The END event indicates that the last bit has been processed by the RADIO. The DISABLED event is issued to acknowledge that a DISABLE task is done.

The structure of a packet is described in detail in Packet configuration. The data that is stored in Data RAM and transported by EasyDMA consists of the following fields:

S0
LENGTH
S1
PAYLOAD

In addition, a static add-on is sent immediately after the payload.

The size of each of the above fields in the frame is configurable (see Packet configuration), and the space occupied in RAM depends on these settings. The size of the field can be zero, as long as the resulting frame complies with the chosen RF protocol.

All fields are extended in size to align with a byte boundary in RAM. For instance, a 3-bit long field on air will occupy 1 byte in RAM while a 9-bit long field will be extended to 2 bytes.

The packet's elements can be configured as follows:

CI, TERM1, and TERM2 fields are only present in Bluetooth Low Energy Long Range mode
S0 is configured through the PCNF0.S0LEN field
LENGTH is configured through the PCNF0.LFLEN field
S1 is configured through the PCNF0.S1LEN field
Payload size is configured through the value in RAM corresponding to the LENGTH field
Static add-on size is configured through the PCNF1.STATLEN field

The PCNF1.MAXLEN field configures the maximum packet payload plus add-on size in number of bytes that can be transmitted or received by the RADIO. This feature can be used to ensure that the RADIO does not overwrite, or read beyond, the RAM assigned to the packet payload. This means that if the LENGTH field of the packet payload exceedes PCNF1.STATLEN, and the LENGTH field in the packet specifies a packet larger than configured in PCNF1.MAXLEN, the payload will be truncated to the length specified in PCNF1.MAXLEN.

Note: The PCNF1.MAXLEN field includes the payload and the add-on, but excludes the size occupied by the S0, LENGTH, and S1 fields. This has to be taken into account when allocating RAM.

If the payload and add-on length is specified larger than PCNF1.MAXLEN, the RADIO will still transmit or receive in the same way as before, except the payload is now truncated to PCNF1.MAXLEN. The packet's LENGTH field will not be altered when the payload is truncated. The RADIO will calculate CRC as if the packet length is equal to PCNF1.MAXLEN.

Note: If PACKETPTR is not pointing to the Data RAM region, an EasyDMA transfer may result in a HardFault or RAM corruption. See Memory for more information about the different memory regions.

The END event indicates that the last bit has been processed by the RADIO. The DISABLED event is issued to acknowledge that an DISABLE task is done.

Registers

Table 10. Instances
Base address	Peripheral	Instance	Description	Configuration
0x40001000	RADIO	RADIO	2.4 GHz radio

Table 11. Register overview
Register	Offset	Description
TASKS_TXEN	0x000	Enable RADIO in TX mode
TASKS_RXEN	0x004	Enable RADIO in RX mode
TASKS_START	0x008	Start RADIO
TASKS_STOP	0x00C	Stop RADIO
TASKS_DISABLE	0x010	Disable RADIO
TASKS_RSSISTART	0x014	Start the RSSI and take one single sample of the receive signal strength
TASKS_RSSISTOP	0x018	Stop the RSSI measurement
TASKS_BCSTART	0x01C	Start the bit counter
TASKS_BCSTOP	0x020	Stop the bit counter
TASKS_EDSTART	0x024	Start the energy detect measurement used in IEEE 802.15.4 mode
TASKS_EDSTOP	0x028	Stop the energy detect measurement
TASKS_CCASTART	0x02C	Start the clear channel assessment used in IEEE 802.15.4 mode
TASKS_CCASTOP	0x030	Stop the clear channel assessment
EVENTS_READY	0x100	RADIO has ramped up and is ready to be started
EVENTS_ADDRESS	0x104	Address sent or received
EVENTS_PAYLOAD	0x108	Packet payload sent or received
EVENTS_END	0x10C	Packet sent or received
EVENTS_DISABLED	0x110	RADIO has been disabled
EVENTS_DEVMATCH	0x114	A device address match occurred on the last received packet
EVENTS_DEVMISS	0x118	No device address match occurred on the last received packet
EVENTS_RSSIEND	0x11C	Sampling of receive signal strength complete
EVENTS_BCMATCH	0x128	Bit counter reached bit count value
EVENTS_CRCOK	0x130	Packet received with CRC ok
EVENTS_CRCERROR	0x134	Packet received with CRC error
EVENTS_FRAMESTART	0x138	IEEE 802.15.4 length field received
EVENTS_EDEND	0x13C	Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register.
EVENTS_EDSTOPPED	0x140	The sampling of energy detection has stopped
EVENTS_CCAIDLE	0x144	Wireless medium in idle - clear to send
EVENTS_CCABUSY	0x148	Wireless medium busy - do not send
EVENTS_CCASTOPPED	0x14C	The CCA has stopped
EVENTS_RATEBOOST	0x150	Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit.
EVENTS_TXREADY	0x154	RADIO has ramped up and is ready to be started TX path
EVENTS_RXREADY	0x158	RADIO has ramped up and is ready to be started RX path
EVENTS_MHRMATCH	0x15C	MAC header match found
EVENTS_SYNC	0x168	Preamble indicator
EVENTS_PHYEND	0x16C	Generated when last bit is sent on air, or received from air
EVENTS_CTEPRESENT	0x170	CTE is present (early warning right after receiving CTEInfo byte)
SHORTS	0x200	Shortcuts between local events and tasks
INTENSET	0x304	Enable interrupt
INTENCLR	0x308	Disable interrupt
CRCSTATUS	0x400	CRC status
RXMATCH	0x408	Received address
RXCRC	0x40C	CRC field of previously received packet
DAI	0x410	Device address match index
PDUSTAT	0x414	Payload status
CTESTATUS	0x44C	CTEInfo parsed from received packet
DFESTATUS	0x458	DFE status information
PACKETPTR	0x504	Packet pointer
FREQUENCY	0x508	Frequency
TXPOWER	0x50C	Output power
MODE	0x510	Data rate and modulation
PCNF0	0x514	Packet configuration register 0
PCNF1	0x518	Packet configuration register 1
BASE0	0x51C	Base address 0
BASE1	0x520	Base address 1
PREFIX0	0x524	Prefixes bytes for logical addresses 0-3
PREFIX1	0x528	Prefixes bytes for logical addresses 4-7
TXADDRESS	0x52C	Transmit address select
RXADDRESSES	0x530	Receive address select
CRCCNF	0x534	CRC configuration
CRCPOLY	0x538	CRC polynomial
CRCINIT	0x53C	CRC initial value
TIFS	0x544	Interframe spacing in µs
RSSISAMPLE	0x548	RSSI sample
STATE	0x550	Current radio state
DATAWHITEIV	0x554	Data whitening initial value
BCC	0x560	Bit counter compare
DAB[n]	0x600	Device address base segment n
DAP[n]	0x620	Device address prefix n
DACNF	0x640	Device address match configuration
MHRMATCHCONF	0x644	Search pattern configuration
MHRMATCHMAS	0x648	Pattern mask
MODECNF0	0x650	Radio mode configuration register 0
SFD	0x660	IEEE 802.15.4 start of frame delimiter
EDCNT	0x664	IEEE 802.15.4 energy detect loop count
EDSAMPLE	0x668	IEEE 802.15.4 energy detect level
CCACTRL	0x66C	IEEE 802.15.4 clear channel assessment control
DFEMODE	0x900	Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD)
CTEINLINECONF	0x904	Configuration for CTE inline mode
DFECTRL1	0x910	Various configuration for Direction finding
DFECTRL2	0x914	Start offset for Direction finding
SWITCHPATTERN	0x928	GPIO patterns to be used for each antenna
CLEARPATTERN	0x92C	Clear the GPIO pattern array for antenna control
PSEL.DFEGPIO[0]	0x930	Pin select for DFE pin 0
PSEL.DFEGPIO[1]	0x934	Pin select for DFE pin 1
PSEL.DFEGPIO[2]	0x938	Pin select for DFE pin 2
PSEL.DFEGPIO[3]	0x93C	Pin select for DFE pin 3
PSEL.DFEGPIO[4]	0x940	Pin select for DFE pin 4
PSEL.DFEGPIO[5]	0x944	Pin select for DFE pin 5
PSEL.DFEGPIO[6]	0x948	Pin select for DFE pin 6
PSEL.DFEGPIO[7]	0x94C	Pin select for DFE pin 7
DFEPACKET.PTR	0x950	Data pointer
DFEPACKET.MAXCNT	0x954	Maximum number of buffer words to transfer
DFEPACKET.AMOUNT	0x958	Number of samples transferred in the last transaction
POWER	0xFFC	Peripheral power control

TASKS_TXEN

Address offset: 0x000

Enable RADIO in TX mode

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	W	TASKS_TXEN										Enable RADIO in TX mode
			Trigger	1								Trigger task

TASKS_RXEN

Address offset: 0x004

Enable RADIO in RX mode

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	W	TASKS_RXEN										Enable RADIO in RX mode
			Trigger	1								Trigger task

TASKS_START

Address offset: 0x008

Start RADIO

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	W	TASKS_START										Start RADIO
			Trigger	1								Trigger task

TASKS_STOP

Address offset: 0x00C

Stop RADIO

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	W	TASKS_STOP										Stop RADIO
			Trigger	1								Trigger task

TASKS_DISABLE

Address offset: 0x010

Disable RADIO

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	W	TASKS_DISABLE										Disable RADIO
			Trigger	1								Trigger task

TASKS_RSSISTART

Address offset: 0x014

Start the RSSI and take one single sample of the receive signal strength

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	W	TASKS_RSSISTART										Start the RSSI and take one single sample of the receive signal strength
			Trigger	1								Trigger task

TASKS_RSSISTOP

Address offset: 0x018

Stop the RSSI measurement

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	W	TASKS_RSSISTOP										Stop the RSSI measurement
			Trigger	1								Trigger task

TASKS_BCSTART

Address offset: 0x01C

Start the bit counter

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	W	TASKS_BCSTART										Start the bit counter
			Trigger	1								Trigger task

TASKS_BCSTOP

Address offset: 0x020

Stop the bit counter

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	W	TASKS_BCSTOP										Stop the bit counter
			Trigger	1								Trigger task

TASKS_EDSTART

Address offset: 0x024

Start the energy detect measurement used in IEEE 802.15.4 mode

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	W	TASKS_EDSTART										Start the energy detect measurement used in IEEE 802.15.4 mode
			Trigger	1								Trigger task

TASKS_EDSTOP

Address offset: 0x028

Stop the energy detect measurement

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	W	TASKS_EDSTOP										Stop the energy detect measurement
			Trigger	1								Trigger task

TASKS_CCASTART

Address offset: 0x02C

Start the clear channel assessment used in IEEE 802.15.4 mode

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	W	TASKS_CCASTART										Start the clear channel assessment used in IEEE 802.15.4 mode
			Trigger	1								Trigger task

TASKS_CCASTOP

Address offset: 0x030

Stop the clear channel assessment

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	W	TASKS_CCASTOP										Stop the clear channel assessment
			Trigger	1								Trigger task

EVENTS_READY

Address offset: 0x100

RADIO has ramped up and is ready to be started

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	EVENTS_READY										RADIO has ramped up and is ready to be started
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_ADDRESS

Address offset: 0x104

Address sent or received

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	EVENTS_ADDRESS										Address sent or received
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_PAYLOAD

Address offset: 0x108

Packet payload sent or received

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	EVENTS_PAYLOAD										Packet payload sent or received
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_END

Address offset: 0x10C

Packet sent or received

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	EVENTS_END										Packet sent or received
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_DISABLED

Address offset: 0x110

RADIO has been disabled

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	EVENTS_DISABLED										RADIO has been disabled
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_DEVMATCH

Address offset: 0x114

A device address match occurred on the last received packet

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	EVENTS_DEVMATCH										A device address match occurred on the last received packet
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_DEVMISS

Address offset: 0x118

No device address match occurred on the last received packet

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	EVENTS_DEVMISS										No device address match occurred on the last received packet
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_RSSIEND

Address offset: 0x11C

Sampling of receive signal strength complete

A new RSSI sample is ready for readout from the RADIO.RSSISAMPLE register

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	EVENTS_RSSIEND										Sampling of receive signal strength complete A new RSSI sample is ready for readout from the RADIO.RSSISAMPLE register
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_BCMATCH

Address offset: 0x128

Bit counter reached bit count value

Bit counter value is specified in the RADIO.BCC register

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	EVENTS_BCMATCH										Bit counter reached bit count value Bit counter value is specified in the RADIO.BCC register
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_CRCOK

Address offset: 0x130

Packet received with CRC ok

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	EVENTS_CRCOK										Packet received with CRC ok
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_CRCERROR

Address offset: 0x134

Packet received with CRC error

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	EVENTS_CRCERROR										Packet received with CRC error
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_FRAMESTART

Address offset: 0x138

IEEE 802.15.4 length field received

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	EVENTS_FRAMESTART										IEEE 802.15.4 length field received
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_EDEND

Address offset: 0x13C

Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register.

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	EVENTS_EDEND										Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register.
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_EDSTOPPED

Address offset: 0x140

The sampling of energy detection has stopped

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	EVENTS_EDSTOPPED										The sampling of energy detection has stopped
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_CCAIDLE

Address offset: 0x144

Wireless medium in idle - clear to send

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	EVENTS_CCAIDLE										Wireless medium in idle - clear to send
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_CCABUSY

Address offset: 0x148

Wireless medium busy - do not send

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	EVENTS_CCABUSY										Wireless medium busy - do not send
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_CCASTOPPED

Address offset: 0x14C

The CCA has stopped

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	EVENTS_CCASTOPPED										The CCA has stopped
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_RATEBOOST

Address offset: 0x150

Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit.

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	EVENTS_RATEBOOST										Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit.
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_TXREADY

Address offset: 0x154

RADIO has ramped up and is ready to be started TX path

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	EVENTS_TXREADY										RADIO has ramped up and is ready to be started TX path
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_RXREADY

Address offset: 0x158

RADIO has ramped up and is ready to be started RX path

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	EVENTS_RXREADY										RADIO has ramped up and is ready to be started RX path
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_MHRMATCH

Address offset: 0x15C

MAC header match found

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	EVENTS_MHRMATCH										MAC header match found
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_SYNC

Address offset: 0x168

Preamble indicator

A possible preamble has been received in Ble_LR125Kbit, Ble_LR500Kbit, or Ieee802154_250Kbit modes during an RX transaction. False triggering of the event is possible.

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	EVENTS_SYNC										Preamble indicator A possible preamble has been received in Ble_LR125Kbit, Ble_LR500Kbit, or Ieee802154_250Kbit modes during an RX transaction. False triggering of the event is possible.
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_PHYEND

Address offset: 0x16C

Generated when last bit is sent on air, or received from air

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	EVENTS_PHYEND										Generated when last bit is sent on air, or received from air
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_CTEPRESENT

Address offset: 0x170

CTE is present (early warning right after receiving CTEInfo byte)

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	EVENTS_CTEPRESENT										CTE is present (early warning right after receiving CTEInfo byte)
			NotGenerated	0								Event not generated
			Generated	1								Event generated

SHORTS

Address offset: 0x200

Shortcuts between local events and tasks

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID														U	T	S	R	Q	P	O	N	M	L	K			H		G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	READY_START										Shortcut between event READY and task START
			Disabled	0								Disable shortcut
			Enabled	1								Enable shortcut
B	RW	END_DISABLE										Shortcut between event END and task DISABLE
			Disabled	0								Disable shortcut
			Enabled	1								Enable shortcut
C	RW	DISABLED_TXEN										Shortcut between event DISABLED and task TXEN
			Disabled	0								Disable shortcut
			Enabled	1								Enable shortcut
D	RW	DISABLED_RXEN										Shortcut between event DISABLED and task RXEN
			Disabled	0								Disable shortcut
			Enabled	1								Enable shortcut
E	RW	ADDRESS_RSSISTART										Shortcut between event ADDRESS and task RSSISTART
			Disabled	0								Disable shortcut
			Enabled	1								Enable shortcut
F	RW	END_START										Shortcut between event END and task START
			Disabled	0								Disable shortcut
			Enabled	1								Enable shortcut
G	RW	ADDRESS_BCSTART										Shortcut between event ADDRESS and task BCSTART
			Disabled	0								Disable shortcut
			Enabled	1								Enable shortcut
H	RW	DISABLED_RSSISTOP										Shortcut between event DISABLED and task RSSISTOP
			Disabled	0								Disable shortcut
			Enabled	1								Enable shortcut
K	RW	RXREADY_CCASTART										Shortcut between event RXREADY and task CCASTART
			Disabled	0								Disable shortcut
			Enabled	1								Enable shortcut
L	RW	CCAIDLE_TXEN										Shortcut between event CCAIDLE and task TXEN
			Disabled	0								Disable shortcut
			Enabled	1								Enable shortcut
M	RW	CCABUSY_DISABLE										Shortcut between event CCABUSY and task DISABLE
			Disabled	0								Disable shortcut
			Enabled	1								Enable shortcut
N	RW	FRAMESTART_BCSTART										Shortcut between event FRAMESTART and task BCSTART
			Disabled	0								Disable shortcut
			Enabled	1								Enable shortcut
O	RW	READY_EDSTART										Shortcut between event READY and task EDSTART
			Disabled	0								Disable shortcut
			Enabled	1								Enable shortcut
P	RW	EDEND_DISABLE										Shortcut between event EDEND and task DISABLE
			Disabled	0								Disable shortcut
			Enabled	1								Enable shortcut
Q	RW	CCAIDLE_STOP										Shortcut between event CCAIDLE and task STOP
			Disabled	0								Disable shortcut
			Enabled	1								Enable shortcut
R	RW	TXREADY_START										Shortcut between event TXREADY and task START
			Disabled	0								Disable shortcut
			Enabled	1								Enable shortcut
S	RW	RXREADY_START										Shortcut between event RXREADY and task START
			Disabled	0								Disable shortcut
			Enabled	1								Enable shortcut
T	RW	PHYEND_DISABLE										Shortcut between event PHYEND and task DISABLE
			Disabled	0								Disable shortcut
			Enabled	1								Enable shortcut
U	RW	PHYEND_START										Shortcut between event PHYEND and task START
			Disabled	0								Disable shortcut
			Enabled	1								Enable shortcut

INTENSET

Address offset: 0x304

Enable interrupt

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID							a	Z	Y			V	U	T	S	R	Q	P	O	N	M	L	K		I			H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	READY										Write '1' to enable interrupt for event READY
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
B	RW	ADDRESS										Write '1' to enable interrupt for event ADDRESS
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
C	RW	PAYLOAD										Write '1' to enable interrupt for event PAYLOAD
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
D	RW	END										Write '1' to enable interrupt for event END
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
E	RW	DISABLED										Write '1' to enable interrupt for event DISABLED
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
F	RW	DEVMATCH										Write '1' to enable interrupt for event DEVMATCH
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
G	RW	DEVMISS										Write '1' to enable interrupt for event DEVMISS
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
H	RW	RSSIEND										Write '1' to enable interrupt for event RSSIEND A new RSSI sample is ready for readout from the RADIO.RSSISAMPLE register
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
I	RW	BCMATCH										Write '1' to enable interrupt for event BCMATCH Bit counter value is specified in the RADIO.BCC register
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
K	RW	CRCOK										Write '1' to enable interrupt for event CRCOK
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
L	RW	CRCERROR										Write '1' to enable interrupt for event CRCERROR
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
M	RW	FRAMESTART										Write '1' to enable interrupt for event FRAMESTART
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
N	RW	EDEND										Write '1' to enable interrupt for event EDEND
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
O	RW	EDSTOPPED										Write '1' to enable interrupt for event EDSTOPPED
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
P	RW	CCAIDLE										Write '1' to enable interrupt for event CCAIDLE
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
Q	RW	CCABUSY										Write '1' to enable interrupt for event CCABUSY
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
R	RW	CCASTOPPED										Write '1' to enable interrupt for event CCASTOPPED
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
S	RW	RATEBOOST										Write '1' to enable interrupt for event RATEBOOST
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
T	RW	TXREADY										Write '1' to enable interrupt for event TXREADY
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
U	RW	RXREADY										Write '1' to enable interrupt for event RXREADY
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
V	RW	MHRMATCH										Write '1' to enable interrupt for event MHRMATCH
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
Y	RW	SYNC										Write '1' to enable interrupt for event SYNC A possible preamble has been received in Ble_LR125Kbit, Ble_LR500Kbit, or Ieee802154_250Kbit modes during an RX transaction. False triggering of the event is possible.
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
Z	RW	PHYEND										Write '1' to enable interrupt for event PHYEND
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
a	RW	CTEPRESENT										Write '1' to enable interrupt for event CTEPRESENT
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled

INTENCLR

Address offset: 0x308

Disable interrupt

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID							a	Z	Y			V	U	T	S	R	Q	P	O	N	M	L	K		I			H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	READY										Write '1' to disable interrupt for event READY
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
B	RW	ADDRESS										Write '1' to disable interrupt for event ADDRESS
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
C	RW	PAYLOAD										Write '1' to disable interrupt for event PAYLOAD
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
D	RW	END										Write '1' to disable interrupt for event END
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
E	RW	DISABLED										Write '1' to disable interrupt for event DISABLED
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
F	RW	DEVMATCH										Write '1' to disable interrupt for event DEVMATCH
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
G	RW	DEVMISS										Write '1' to disable interrupt for event DEVMISS
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
H	RW	RSSIEND										Write '1' to disable interrupt for event RSSIEND A new RSSI sample is ready for readout from the RADIO.RSSISAMPLE register
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
I	RW	BCMATCH										Write '1' to disable interrupt for event BCMATCH Bit counter value is specified in the RADIO.BCC register
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
K	RW	CRCOK										Write '1' to disable interrupt for event CRCOK
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
L	RW	CRCERROR										Write '1' to disable interrupt for event CRCERROR
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
M	RW	FRAMESTART										Write '1' to disable interrupt for event FRAMESTART
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
N	RW	EDEND										Write '1' to disable interrupt for event EDEND
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
O	RW	EDSTOPPED										Write '1' to disable interrupt for event EDSTOPPED
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
P	RW	CCAIDLE										Write '1' to disable interrupt for event CCAIDLE
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
Q	RW	CCABUSY										Write '1' to disable interrupt for event CCABUSY
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
R	RW	CCASTOPPED										Write '1' to disable interrupt for event CCASTOPPED
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
S	RW	RATEBOOST										Write '1' to disable interrupt for event RATEBOOST
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
T	RW	TXREADY										Write '1' to disable interrupt for event TXREADY
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
U	RW	RXREADY										Write '1' to disable interrupt for event RXREADY
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
V	RW	MHRMATCH										Write '1' to disable interrupt for event MHRMATCH
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
Y	RW	SYNC										Write '1' to disable interrupt for event SYNC A possible preamble has been received in Ble_LR125Kbit, Ble_LR500Kbit, or Ieee802154_250Kbit modes during an RX transaction. False triggering of the event is possible.
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
Z	RW	PHYEND										Write '1' to disable interrupt for event PHYEND
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
a	RW	CTEPRESENT										Write '1' to disable interrupt for event CTEPRESENT
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled

CRCSTATUS

Address offset: 0x400

CRC status

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	R	CRCSTATUS										CRC status of packet received
			CRCError	0								Packet received with CRC error
			CRCOk	1								Packet received with CRC ok

RXMATCH

Address offset: 0x408

Received address

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	R	RXMATCH										Received address Logical address of which previous packet was received

RXCRC

Address offset: 0x40C

CRC field of previously received packet

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID												A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	R	RXCRC										CRC field of previously received packet CRC field of previously received packet

DAI

Address offset: 0x410

Device address match index

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	R	DAI										Device address match index Index (n) of device address, see DAB[n] and DAP[n], that got an address match

PDUSTAT

Address offset: 0x414

Payload status

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																	B	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	R	PDUSTAT										Status on payload length vs. PCNF1.MAXLEN
			LessThan	0								Payload less than PCNF1.MAXLEN
			GreaterThan	1								Payload greater than PCNF1.MAXLEN
B	R	CISTAT										Status on what rate packet is received with in Long Range
			LR125kbit	0								Frame is received at 125 kbps
			LR500kbit	1								Frame is received at 500 kbps

CTESTATUS

Address offset: 0x44C

CTEInfo parsed from received packet

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																												C	C	B	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	R	CTETIME										CTETime parsed from packet
B	R	RFU										RFU parsed from packet
C	R	CTETYPE										CTEType parsed from packet

DFESTATUS

Address offset: 0x458

DFE status information

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																															B		A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	R	SWITCHINGSTATE										Internal state of switching state machine
			Idle	0								Switching state Idle
			Offset	1								Switching state Offset
			Guard	2								Switching state Guard
			Ref	3								Switching state Ref
			Switching	4								Switching state Switching
			Ending	5								Switching state Ending
B	R	SAMPLINGSTATE										Internal state of sampling state machine
			Idle	0								Sampling state Idle
			Sampling	1								Sampling state Sampling

PACKETPTR

Address offset: 0x504

Packet pointer

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	PACKETPTR										Packet pointer Packet address to be used for the next transmission or reception. When transmitting, the packet pointed to by this address will be transmitted and when receiving, the received packet will be written to this address. This address is a byte aligned RAM address. See the memory chapter for details about which memories are avilable for EasyDMA.

FREQUENCY

Address offset: 0x508

Frequency

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																											B		A	A	A	A	A	A	A
Reset 0x00000002				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0
ID	Access	Field	Value ID	Value								Description
A	RW	FREQUENCY		[0..100]								Radio channel frequency Frequency = 2400 + FREQUENCY (MHz)
B	RW	MAP										Channel map selection
			Default	0								Channel map between 2400 MHZ .. 2500 MHz Frequency = 2400 + FREQUENCY (MHz)
			Low	1								Channel map between 2360 MHZ .. 2460 MHz Frequency = 2360 + FREQUENCY (MHz)

TXPOWER

Address offset: 0x50C

Output power

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																												A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	TXPOWER										RADIO output power Output power in number of dBm, i.e. if the value -20 is specified the output power will be set to -20 dBm.
			Pos8dBm	0x8								+8 dBm
			Pos7dBm	0x7								+7 dBm
			Pos6dBm	0x6								+6 dBm
			Pos5dBm	0x5								+5 dBm
			Pos4dBm	0x4								+4 dBm
			Pos3dBm	0x3								+3 dBm
			Pos2dBm	0x2								+2 dBm
			0dBm	0x0								0 dBm
			Neg4dBm	0xFC								-4 dBm
			Neg8dBm	0xF8								-8 dBm
			Neg12dBm	0xF4								-12 dBm
			Neg16dBm	0xF0								-16 dBm
			Neg20dBm	0xEC								-20 dBm
			Neg30dBm	0xE2								-40 dBm																				Deprecated
			Neg40dBm	0xD8								-40 dBm

MODE

Address offset: 0x510

Data rate and modulation

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	MODE										Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation.
			Nrf_1Mbit	0								1 Mbps Nordic proprietary radio mode
			Nrf_2Mbit	1								2 Mbps Nordic proprietary radio mode
			Ble_1Mbit	3								1 Mbps BLE
			Ble_2Mbit	4								2 Mbps BLE
			Ble_LR125Kbit	5								Long range 125 kbps TX, 125 kbps and 500 kbps RX
			Ble_LR500Kbit	6								Long range 500 kbps TX, 125 kbps and 500 kbps RX
			Ieee802154_250Kbit	15								IEEE 802.15.4-2006 250 kbps

PCNF0

Address offset: 0x514

Packet configuration register 0

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID					J	J			I	H	H	G	G		F	E	E	E	E								C					A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	LFLEN										Length on air of LENGTH field in number of bits
C	RW	S0LEN										Length on air of S0 field in number of bytes
E	RW	S1LEN										Length on air of S1 field in number of bits
F	RW	S1INCL										Include or exclude S1 field in RAM
			Automatic	0								Include S1 field in RAM only if S1LEN > 0
			Include	1								Always include S1 field in RAM independent of S1LEN
G	RW	CILEN										Length of code indicator - long range
H	RW	PLEN										Length of preamble on air. Decision point: TASKS_START task
			8bit	0								8-bit preamble
			16bit	1								16-bit preamble
			32bitZero	2								32-bit zero preamble - used for IEEE 802.15.4
			LongRange	3								Preamble - used for BLE long range
I	RW	CRCINC										Indicates if LENGTH field contains CRC or not
			Exclude	0								LENGTH does not contain CRC
			Include	1								LENGTH includes CRC
J	RW	TERMLEN										Length of TERM field in Long Range operation

PCNF1

Address offset: 0x518

Packet configuration register 1

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID										E	D						C	C	C	B	B	B	B	B	B	B	B	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	MAXLEN		[0..255]								Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN.
B	RW	STATLEN		[0..255]								Static length in number of bytes The static length parameter is added to the total length of the payload when sending and receiving packets, e.g. if the static length is set to N the radio will receive or send N bytes more than what is defined in the LENGTH field of the packet.
C	RW	BALEN		[2..4]								Base address length in number of bytes The address field is composed of the base address and the one byte long address prefix, e.g. set BALEN=2 to get a total address of 3 bytes.
D	RW	ENDIAN										On-air endianness of packet, this applies to the S0, LENGTH, S1, and the PAYLOAD fields.
			Little	0								Least significant bit on air first
			Big	1								Most significant bit on air first
E	RW	WHITEEN										Enable or disable packet whitening
			Disabled	0								Disable
			Enabled	1								Enable

BASE0

Address offset: 0x51C

Base address 0

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	BASE0										Base address 0

BASE1

Address offset: 0x520

Base address 1

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	BASE1										Base address 1

PREFIX0

Address offset: 0x524

Prefixes bytes for logical addresses 0-3

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				D	D	D	D	D	D	D	D	C	C	C	C	C	C	C	C	B	B	B	B	B	B	B	B	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A-D	RW	AP[i] (i=0..3)										Address prefix i.

PREFIX1

Address offset: 0x528

Prefixes bytes for logical addresses 4-7

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				D	D	D	D	D	D	D	D	C	C	C	C	C	C	C	C	B	B	B	B	B	B	B	B	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A-D	RW	AP[i] (i=4..7)										Address prefix i.

TXADDRESS

Address offset: 0x52C

Transmit address select

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	TXADDRESS										Transmit address select Logical address to be used when transmitting a packet

RXADDRESSES

Address offset: 0x530

Receive address select

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																												H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A-H	RW	ADDR[i] (i=0..7)										Enable or disable reception on logical address i.
			Disabled	0								Disable
			Enabled	1								Enable

CRCCNF

Address offset: 0x534

CRC configuration

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																										B	B							A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	LEN		[1..3]								CRC length in number of bytes For MODE Ble_LR125Kbit and Ble_LR500Kbit, only LEN set to 3 is supported
			Disabled	0								CRC length is zero and CRC calculation is disabled
			One	1								CRC length is one byte and CRC calculation is enabled
			Two	2								CRC length is two bytes and CRC calculation is enabled
			Three	3								CRC length is three bytes and CRC calculation is enabled
B	RW	SKIPADDR										Include or exclude packet address field out of CRC calculation.
			Include	0								CRC calculation includes address field
			Skip	1								CRC calculation does not include address field. The CRC calculation will start at the first byte after the address.
			Ieee802154	2								CRC calculation as per 802.15.4 standard. Starting at first byte after length field.

CRCPOLY

Address offset: 0x538

CRC polynomial

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID												A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	CRCPOLY										CRC polynomial Each term in the CRC polynomial is mapped to a bit in this register which index corresponds to the term's exponent. The least significant term/bit is hardwired internally to 1, and bit number 0 of the register content is ignored by the hardware. The following example is for an 8 bit CRC polynomial: x8 + x7 + x3 + x2 + 1 = 1 1000 1101 .

CRCINIT

Address offset: 0x53C

CRC initial value

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID												A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	CRCINIT										CRC initial value Initial value for CRC calculation

TIFS

Address offset: 0x544

Interframe spacing in µs

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																										A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	TIFS										Interframe spacing in µs. Interframe space is the time interval between two consecutive packets. It is defined as the time, in microseconds, from the end of the last bit of the previous packet to the start of the first bit of the subsequent packet.

RSSISAMPLE

Address offset: 0x548

RSSI sample

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																													A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	R	RSSISAMPLE		[0..127]								RSSI sample. RSSI sample result. The value of this register is read as a positive value while the actual received signal strength is a negative value. Actual received signal strength is therefore as follows: received signal strength = -A dBm.

STATE

Address offset: 0x550

Current radio state

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	R	STATE										Current radio state
			Disabled	0								RADIO is in the Disabled state
			RxRu	1								RADIO is in the RXRU state
			RxIdle	2								RADIO is in the RXIDLE state
			Rx	3								RADIO is in the RX state
			RxDisable	4								RADIO is in the RXDISABLED state
			TxRu	9								RADIO is in the TXRU state
			TxIdle	10								RADIO is in the TXIDLE state
			Tx	11								RADIO is in the TX state
			TxDisable	12								RADIO is in the TXDISABLED state

DATAWHITEIV

Address offset: 0x554

Data whitening initial value

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																													A	A	A	A	A	A	A
Reset 0x00000040				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	DATAWHITEIV										Data whitening initial value. Bit 6 is hardwired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. Bit 0 corresponds to Position 6 of the LSFR, Bit 1 to Position 5, etc.

BCC

Address offset: 0x560

Bit counter compare

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	BCC										Bit counter compare Bit counter compare register

DAB[n] (n=0..7)

Address offset: 0x600 + (n × 0x4)

Device address base segment n

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	DAB										Device address base segment n

DAP[n] (n=0..7)

Address offset: 0x620 + (n × 0x4)

Device address prefix n

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	DAP										Device address prefix n

DACNF

Address offset: 0x640

Device address match configuration

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																				P	O	N	M	L	K	J	I	H	G	F	E	D	C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A-H	RW	ENA[i] (i=0..7)										Enable or disable device address matching using device address i
			Disabled	0								Disabled
			Enabled	1								Enabled
I-P	RW	TXADD[i] (i=0..7)										TxAdd for device address i

MHRMATCHCONF

Address offset: 0x644

Search pattern configuration

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	MHRMATCHCONF										Search pattern configuration

MHRMATCHMAS

Address offset: 0x648

Pattern mask

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	MHRMATCHMAS										Pattern mask

MODECNF0

Address offset: 0x650

Radio mode configuration register 0

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																										C	C								A
Reset 0x00000200				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	RU										Radio ramp-up time
			Default	0								Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51
			Fast	1								Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specifications for more information When enabled, TIFS is not enforced by hardware and software needs to control when to turn on the Radio
C	RW	DTX										Default TX value Specifies what the RADIO will transmit when it is not started, i.e. between: RADIO.EVENTS_READY and RADIO.TASKS_START RADIO.EVENTS_END and RADIO.TASKS_START RADIO.EVENTS_END and RADIO.EVENTS_DISABLED For IEEE 802.15.4 250 kbps mode only Center is a valid setting For Bluetooth Low Energy Long Range mode only Center is a valid setting
			B1	0								Transmit '1'
			B0	1								Transmit '0'
			Center	2								Transmit center frequency When tuning the crystal for center frequency, the RADIO must be set in DTX = Center mode to be able to achieve the expected accuracy

SFD

Address offset: 0x660

IEEE 802.15.4 start of frame delimiter

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																												A	A	A	A	A	A	A	A
Reset 0x000000A7				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	1	0	0	1	1	1
ID	Access	Field	Value ID	Value								Description
A	RW	SFD										IEEE 802.15.4 start of frame delimiter

EDCNT

Address offset: 0x664

IEEE 802.15.4 energy detect loop count

Number of iterations to perform an ED scan. If set to 0 one scan is performed, otherwise the specified number + 1 of ED scans will be performed and the max ED value tracked in EDSAMPLE.

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID															A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	EDCNT										IEEE 802.15.4 energy detect loop count

EDSAMPLE

Address offset: 0x668

IEEE 802.15.4 energy detect level

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																												A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	R	EDLVL		[0..127]								IEEE 802.15.4 energy detect level Register value must be converted to IEEE 802.15.4 range by an 8-bit saturating multiplication by factor ED_RSSISCALE, as shown in the code example for ED sampling

CCACTRL

Address offset: 0x66C

IEEE 802.15.4 clear channel assessment control

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				D	D	D	D	D	D	D	D	C	C	C	C	C	C	C	C	B	B	B	B	B	B	B	B						A	A	A
Reset 0x052D0000				0	0	0	0	0	1	0	1	0	0	1	0	1	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	CCAMODE										CCA mode of operation
			EdMode	0								Energy above threshold Will report busy whenever energy is detected above CCAEDTHRES
			CarrierMode	1								Carrier seen Will report busy whenever compliant IEEE 802.15.4 signal is seen
			CarrierAndEdMode	2								Energy above threshold AND carrier seen
			CarrierOrEdMode	3								Energy above threshold OR carrier seen
			EdModeTest1	4								Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging.
B	RW	CCAEDTHRES										CCA energy busy threshold. Used in all the CCA modes except CarrierMode. Must be converted from IEEE 802.15.4 range by dividing by factor ED_RSSISCALE - similar to EDSAMPLE register
C	RW	CCACORRTHRES										CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode, and CarrierOrEdMode.
D	RW	CCACORRCNT										Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled.

DFEMODE

Address offset: 0x900

Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD)

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																		A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	DFEOPMODE										Direction finding operation mode
			Disabled	0								Direction finding mode disabled
			AoD	2								Direction finding mode set to AoD
			AoA	3								Direction finding mode set to AoA

CTEINLINECONF

Address offset: 0x904

Configuration for CTE inline mode

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				I	I	I	I	I	I	I	I	H	H	H	H	H	H	H	H	G	G	G	F	F	F			E	E		C	B			A
Reset 0x00002800				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	CTEINLINECTRLEN										Enable parsing of CTEInfo from received packet in BLE modes
			Enabled	1								Parsing of CTEInfo is enabled
			Disabled	0								Parsing of CTEInfo is disabled
B	RW	CTEINFOINS1										CTEInfo is S1 byte or not
			InS1	1								CTEInfo is in S1 byte (data PDU)
			NotInS1	0								CTEInfo is NOT in S1 byte (advertising PDU)
C	RW	CTEERRORHANDLING										Sampling/switching if CRC is not OK
			Yes	1								Sampling and antenna switching also when CRC is not OK
			No	0								No sampling and antenna switching when CRC is not OK
E	RW	CTETIMEVALIDRANGE										Max range of CTETime Valid range is 2-20 in BLE core spec. If larger than 20, it can be an indication of an error in the received packet.
			20	0								20 in 8 µs unit (default) Set to 20 if parsed CTETime is larger than 20
			31	1								31 in 8 µs unit
			63	2								63 in 8 µs unit
F	RW	CTEINLINERXMODE1US										Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. When the device is in AoD mode, this is used when the received CTEType is "AoD 1 µs". When in AoA mode, this is used when TSWITCHSPACING is 2 µs.
			4us	1								4 µs
			2us	2								2 µs
			1us	3								1 µs
			500ns	4								0.5 µs
			250ns	5								0.25 µs
			125ns	6								0.125 µs
G	RW	CTEINLINERXMODE2US										Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. When the device is in AoD mode, this is used when the received CTEType is "AoD 2 µs". When in AoA mode, this is used when TSWITCHSPACING is 4 µs.
			4us	1								4 µs
			2us	2								2 µs
			1us	3								1 µs
			500ns	4								0.5 µs
			250ns	5								0.25 µs
			125ns	6								0.125 µs
H	RW	S0CONF										S0 bit pattern to match The least significant bit always corresponds to the first bit of S0 received.
I	RW	S0MASK										S0 bit mask to set which bit to match The least significant bit always corresponds to the first bit of S0 received.

DFECTRL1

Address offset: 0x910

Various configuration for Direction finding

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID								I	I	I	I	H	H	H	H		G	G	G	F	E	E	E		C	C	C	B		A	A	A	A	A	A
Reset 0x00023282				0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	1	1	0	0	1	0	1	0	0	0	0	0	1	0
ID	Access	Field	Value ID	Value								Description
A	RW	NUMBEROF8US										Length of the AoA/AoD procedure in number of 8 µs units Always used in TX mode, but in RX mode only when CTEINLINECTRLEN is 0
B	RW	DFEINEXTENSION										Add CTE extension and do antenna switching/sampling in this extension
			CRC	1								AoA/AoD procedure triggered at end of CRC
			Payload	0								Antenna switching/sampling is done in the packet payload
C	RW	TSWITCHSPACING										Interval between every time the antenna is changed in the SWITCHING state
			4us	1								4 µs
			2us	2								2 µs
			1us	3								1 µs
E	RW	TSAMPLESPACINGREF										Interval between samples in the REFERENCE period
			4us	1								4 µs
			2us	2								2 µs
			1us	3								1 µs
			500ns	4								0.5 µs
			250ns	5								0.25 µs
			125ns	6								0.125 µs
F	RW	SAMPLETYPE										Whether to sample I/Q or magnitude/phase
			IQ	0								Complex samples in I and Q
			MagPhase	1								Complex samples as magnitude and phase
G	RW	TSAMPLESPACING										Interval between samples in the SWITCHING period when CTEINLINECTRLEN is 0 Not used when CTEINLINECTRLEN is set. Then either CTEINLINERXMODE1US or CTEINLINERXMODE2US are used.
			4us	1								4 µs
			2us	2								2 µs
			1us	3								1 µs
			500ns	4								0.5 µs
			250ns	5								0.25 µs
			125ns	6								0.125 µs
H	RW	REPEATPATTERN										Repeat each individual antenna pattern N times sequentially, i.e. P0, P0, P1, P1, P2, P2, P3, P3, etc.
			NoRepeat	0								Do not repeat (1 time in total)
I	RW	AGCBACKOFFGAIN										Gain will be lowered by the specified number of gain steps at the start of CTE First LNAGAIN gain drops, then MIXGAIN, then AAFGAIN

DFECTRL2

Address offset: 0x914

Start offset for Direction finding

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID								B	B	B	B	B	B	B	B	B	B	B	B				A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	TSWITCHOFFSET										Signed value offset after the end of the CRC before starting switching in number of 16M cycles Decreasing TSWITCHOFFSET beyond the trigger of the AoA/AoD procedure will have no effect
B	RW	TSAMPLEOFFSET										Signed value offset before starting sampling in number of 16M cycles relative to the beginning of the REFERENCE state - 12 µs after switching start Decreasing TSAMPLEOFFSET beyond the trigger of the AoA/AoD procedure will have no effect

SWITCHPATTERN

Address offset: 0x928

GPIO patterns to be used for each antenna

Maximum 8 GPIOs can be controlled. To secure correct signal levels on the pins, the pins must be configured in the GPIO peripheral as described in Pin configuration.

If, during switching, the total number of antenna slots is bigger than the number of written patterns, the RADIO loops back to the pattern used after the reference pattern.

A minimum number of three patterns must be written.

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																												A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	SWITCHPATTERN										Fill array of GPIO patterns for antenna control. The GPIO pattern array size is 40 entries. When written, bit n corresponds to the GPIO configured in PSEL.DFEGPIO[n]. When read, returns the number of GPIO patterns written since the last time the array was cleared. Use CLEARPATTERN to clear the array.

CLEARPATTERN

Address offset: 0x92C

Clear the GPIO pattern array for antenna control

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	CLEARPATTERN										Clears GPIO pattern array for antenna control
			Clear	1								Clear the GPIO pattern

PSEL.DFEGPIO[n] (n=0..7)

Address offset: 0x930 + (n × 0x4)

Pin select for DFE pin n

Must be set before enabling the radio

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				C																										B	A	A	A	A	A
Reset 0xFFFFFFFF				1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
ID	Access	Field	Value ID	Value								Description
A	RW	PIN		[0..31]								Pin number
B	RW	PORT		[0..1]								Port number
C	RW	CONNECT										Connection
			Disconnected	1								Disconnect
			Connected	0								Connect

DFEPACKET.PTR

Address offset: 0x950

Data pointer

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	PTR										Data pointer See the memory chapter for details about which memories are available for EasyDMA.

DFEPACKET.MAXCNT

Address offset: 0x954

Maximum number of buffer words to transfer

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																						A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00001000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	RW	MAXCNT										Maximum number of buffer words to transfer

DFEPACKET.AMOUNT

Address offset: 0x958

Number of samples transferred in the last transaction

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																				A	A	A	A	A	A	A	A	A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	Access	Field	Value ID	Value								Description
A	R	AMOUNT										Number of samples transferred in the last transaction

POWER

Address offset: 0xFFC

Peripheral power control

Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000001				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1
ID	Access	Field	Value ID	Value								Description
A	RW	POWER										Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again.
			Disabled	0								Peripheral is powered off
			Enabled	1								Peripheral is powered on

Electrical specification

General radio characteristics

Symbol	Description	Min.	Typ.	Max.	Units
f_OP	Operating frequencies	2360		2500	MHz
f_PLL,CH,SP	PLL channel spacing		1		MHz
f_DELTA,1M	Frequency deviation @ 1 Mbps		±170		kHz
f_DELTA,BLE,1M	Frequency deviation @ BLE 1 Mbps		±250		kHz
f_DELTA,2M	Frequency deviation @ 2 Mbps		±320		kHz
f_DELTA,BLE,2M	Frequency deviation @ BLE 2 Mbps		±500		kHz
fsk_BPS	On-the-air data rate	125		2000	kbps
f_{chip, IEEE 802.15.4}	Chip rate in IEEE 802.15.4 mode		2000		kchip/s

Radio current consumption (transmitter)

Symbol	Description	Typ.	Units
I_{TX,PLUS8dBM,DCDC}	TX only run current (DC/DC, 3 V) P_RF = +8 dBm	14.2	mA
I_TX,PLUS8dBM	TX only run current P_RF = +8 dBm	30.4	mA
I_{TX,PLUS4dBM,DCDC}	TX only run current (DC/DC, 3 V) P_RF = +4 dBm	9.6	mA
I_TX,PLUS4dBM	TX only run current P_RF = +4 dBm	20.7	mA
I_TX,0dBM,DCDC	TX only run current (DC/DC, 3 V)P_RF = 0 dBm	4.9	mA
I_TX,0dBM	TX only run current P_RF = 0 dBm	10.3	mA
I_{TX,MINUS4dBM,DCDC}	TX only run current DC/DC, 3 V P_RF = -4 dBm	3.8	mA
I_TX,MINUS4dBM	TX only run current P_RF = -4 dBm	8.0	mA
I_{TX,MINUS8dBM,DCDC}	TX only run current DC/DC, 3 V P_RF = -8 dBm	3.4	mA
I_TX,MINUS8dBM	TX only run current P_RF = -8 dBm	7.1	mA
I_{TX,MINUS12dBM,DCDC}	TX only run current DC/DC, 3 V P_RF = -12 dBm	3.1	mA
I_{TX,MINUS12dBM}	TX only run current P_RF = -12 dBm	6.4	mA
I_{TX,MINUS16dBM,DCDC}	TX only run current DC/DC, 3 V P_RF = -16 dBm	2.9	mA
I_{TX,MINUS16dBM}	TX only run current P_RF = -16 dBm	5.9	mA
I_{TX,MINUS20dBM,DCDC}	TX only run current DC/DC, 3 V P_RF = -20 dBm	2.7	mA
I_{TX,MINUS20dBM}	TX only run current P_RF = -20 dBm	5.5	mA
I_{TX,MINUS40dBM,DCDC}	TX only run current DC/DC, 3 V P_RF = -40 dBm	2.3	mA
I_{TX,MINUS40dBM}	TX only run current P_RF = -40 dBm	4.5	mA
I_{START,TX,DCDC}	TX start-up current DC/DC, 3 V, P_RF = 4 dBm	4.3	mA
I_START,TX	TX start-up current, P_RF = 4 dBm	8.9	mA

Radio current consumption (Receiver)

Symbol	Description	Typ.	Units
I_RX,1M,DCDC	RX only run current (DC/DC, 3 V) 1 Mbps/1 Mbps BLE	4.6	mA
I_RX,1M	RX only run current (LDO, 3 V) 1 Mbps/1 Mbps BLE	9.6	mA
I_RX,2M,DCDC	RX only run current (DC/DC, 3 V) 2 Mbps/2 Mbps BLE	5.2	mA
I_RX,2M	RX only run current (LDO, 3 V) 2 Mbps/2 Mbps BLE	10.7	mA
I_{START,RX,1M,DCDC}	RX start-up current (DC/DC, 3 V) 1 Mbps/1 Mbps BLE	3.4	mA
I_START,RX,1M	RX start-up current 1 Mbps/1 Mbps BLE	6.8	mA

Transmitter specification

Symbol	Description	Typ.	Max.	Units
P_RF	Maximum output power	8		dBm
P_RFC	RF power control range	28		dB
P_RFCR	RF power accuracy		±4	dB
P_RF1,1	1st Adjacent Channel Transmit Power 1 MHz (1 Mbps)	-25		dBc
P_RF2,1	2nd Adjacent Channel Transmit Power 2 MHz (1 Mbps)	-54		dBc
P_RF1,2	1st Adjacent Channel Transmit Power 2 MHz (2 Mbps)	-26		dBc
P_RF2,2	2nd Adjacent Channel Transmit Power 4 MHz (2 Mbps)	-54		dBc
E_vm	Error vector magnitude in IEEE 802.15.4 mode	9		%rms
P_{harm2nd, IEEE 802.15.4}	2nd harmonics in IEEE 802.15.4 mode	-51		dBm
P_{harm3rd, IEEE 802.15.4}	3rd harmonics in IEEE 802.15.4 mode	-51		dBm

Figure 31. Output power, 1 Mbps Bluetooth low energy mode, at maximum TXPOWER setting (typical values)

Figure 32. Output power, 1 Mbps Bluetooth low energy mode, at 0 dBm TXPOWER setting (typical values)

Receiver operation

Symbol	Description	Typ.	Units
P_RX,MAX	Maximum received signal strength at < 0.1% PER	0	dBm
P_SENS,IT,1M	Sensitivity, 1 Mbps nRF mode ideal transmitter ¹	-93	dBm
P_SENS,IT,2M	Sensitivity, 2 Mbps nRF mode ideal transmitter ¹	-89	dBm
P_{SENS,IT,SP,1M,BLE}	Sensitivity, 1 Mbps BLE ideal transmitter, packet length ≤ 37 bytes BER=1E-3²	-96	dBm
P_{SENS,IT,LP,1M,BLE}	Sensitivity, 1 Mbps BLE ideal transmitter, packet length ≥ 128 bytes BER=1E-4 ³	-94	dBm
P_{SENS,IT,SP,2M,BLE}	Sensitivity, 2 Mbps BLE ideal transmitter, packet length ≤ 37 bytes	-92	dBm
P_{SENS,IT,BLE LE125k}	Sensitivity, 125 kbps BLE mode	-103	dBm
P_{SENS,IT,BLE LE500k}	Sensitivity, 500 kbps BLE mode	-98	dBm
P_{SENS,IEEE 802.15.4}	Sensitivity in IEEE 802.15.4 mode	-100	dBm

Figure 33. Sensitivity, 1 Mbps Bluetooth low energy mode, Regulator = LDO (typical values)

RX selectivity

RX selectivity with equal modulation on interfering signal⁴

Symbol	Description	Typ.	Units
C/I_{1M,co-channel}	1Mbps mode, co-channel interference	10	dB
C/I_1M,-1MHz	1 Mbps mode, Adjacent (-1 MHz) interference	-5	dB
C/I_1M,+1MHz	1 Mbps mode, Adjacent (+1 MHz) interference	-14	dB
C/I_1M,-2MHz	1 Mbps mode, Adjacent (-2 MHz) interference	-19	dB
C/I_1M,+2MHz	1 Mbps mode, Adjacent (+2 MHz) interference	-42	dB
C/I_1M,-3MHz	1 Mbps mode, Adjacent (-3 MHz) interference	-37	dB
C/I_1M,+3MHz	1 Mbps mode, Adjacent (+3 MHz) interference	-47	dB
C/I_1M,±6MHz	1 Mbps mode, Adjacent (≥6 MHz) interference	-52	dB
C/I_{1MBLE,co-channel}	1 Mbps BLE mode, co-channel interference	6	dB
C/I_1MBLE,-1MHz	1 Mbps BLE mode, Adjacent (-1 MHz) interference	-2	dB
C/I_1MBLE,+1MHz	1 Mbps BLE mode, Adjacent (+1 MHz) interference	-10	dB
C/I_1MBLE,-2MHz	1 Mbps BLE mode, Adjacent (-2 MHz) interference	-23	dB
C/I_1MBLE,+2MHz	1 Mbps BLE mode, Adjacent (+2 MHz) interference	-45	dB
C/I_1MBLE,>3MHz	1 Mbps BLE mode, Adjacent (≥3 MHz) interference	-54	dB
C/I_1MBLE,image	Image frequency interference	-24	dB
C/I_{1MBLE,image,1MHz}	Adjacent (1 MHz) interference to in-band image frequency	-37	dB
C/I_{2M,co-channel}	2 Mbps mode, co-channel interference	10	dB
C/I_2M,-2MHz	2 Mbps mode, Adjacent (-2 MHz) interference	-4	dB
C/I_2M,+2MHz	2 Mbps mode, Adjacent (+2 MHz) interference	-16	dB
C/I_2M,-4MHz	2 Mbps mode, Adjacent (-4 MHz) interference	-19	dB
C/I_2M,+4MHz	2 Mbps mode, Adjacent (+4 MHz) interference	-46	dB
C/I_2M,-6MHz	2 Mbps mode, Adjacent (-6 MHz) interference	-41	dB
C/I_2M,+6MHz	2 Mbps mode, Adjacent (+6 MHz) interference	-48	dB
C/I_2M,≥12MHz	2 Mbps mode, Adjacent (≥12 MHz) interference	-52	dB
C/I_{2MBLE,co-channel}	2 Mbps BLE mode, co-channel interference	7	dB
C/I_2MBLE,-2MHz	2 Mbps BLE mode, Adjacent (-2 MHz) interference	-2	dB
C/I_2MBLE,+2MHz	2 Mbps BLE mode, Adjacent (+2 MHz) interference	-12	dB
C/I_2MBLE,-4MHz	2 Mbps BLE mode, Adjacent (-4 MHz) interference	-22	dB
C/I_2MBLE,+4MHz	2 Mbps BLE mode, Adjacent (+4 MHz) interference	-46	dB
C/I_{2MBLE,≥6MHz}	2 Mbps BLE mode, Adjacent (≥6 MHz) interference	-52	dB
C/I_2MBLE,image	Image frequency interference	-22	dB
C/I_{2MBLE,image, 2MHz}	Adjacent (2 MHz) interference to in-band image frequency	-37	dB
C/I_{125k BLE LR,co-channel}	125 kbps BLE LR mode, co-channel interference	3	dB
C/I_{125k BLE LR,-1MHz}	125 kbps BLE LR mode, Adjacent (-1 MHz) interference	-9	dB
C/I_{125k BLE LR,+1MHz}	125 kbps BLE LR mode, Adjacent (+1 MHz) interference	-16	dB
C/I_{125k BLE LR,-2MHz}	125 kbps BLE LR mode, Adjacent (-2 MHz) interference	-27	dB
C/I_{125k BLE LR,+2MHz}	125 kbps BLE LR mode, Adjacent (+2 MHz) interference	-54	dB
C/I_{125k BLE LR,>3MHz}	125 kbps BLE LR mode, Adjacent (≥3 MHz) interference	-60	dB
C/I_{125k BLE LR,image}	Image frequency interference	-27	dB
C/I_{IEEE 802.15.4,-5MHz}	IEEE 802.15.4 mode, Adjacent (-5 MHz) rejection	-33	dB
C/I_{IEEE 802.15.4,+5MHz}	IEEE 802.15.4 mode, Adjacent (+5 MHz) rejection	-38	dB
C/I_{IEEE 802.15.4,±10MHz}	IEEE 802.15.4 mode, Alternate (±10 MHz) rejection	-49	dB

RX intermodulation

RX intermodulation. Desired signal level at PIN = -64 dBm. Two interferers with equal input power are used. The interferer closest in frequency is not modulated, the other interferer is modulated equal with the desired signal. The input power of the interferers where the sensitivity equals BER = 0.1% is presented.

Symbol	Description	Typ.	Units
P_IMD,5TH,1M	IMD performance, 1 Mbps, 5th offset channel, packet length ≤ 37 bytes	-34	dBm
P_{IMD,5TH,1M,BLE}	IMD performance, BLE 1 Mbps, 5th offset channel, packet length ≤ 37 bytes	-32	dBm
P_IMD,5TH,2M	IMD performance, 2 Mbps, 5th offset channel, packet length ≤ 37 bytes	-33	dBm
P_{IMD,5TH,2M,BLE}	IMD performance, BLE 2 Mbps, 5th offset channel, packet length ≤ 37 bytes	-32	dBm

Radio timing

Symbol	Description	Min.	Typ.	Max.	Units
t_TXEN,BLE,1M	Time between TXEN task and READY event after channel FREQUENCY configured (1 Mbps BLE and 150 µs TIFS)	140		140	µs
t_{TXEN,FAST,BLE,1M}	Time between TXEN task and READY event after channel FREQUENCY configured (1 Mbps BLE with fast ramp-up and 150 µs TIFS)	40		40	µs
t_TXDIS,BLE,1M	When in TX, delay between DISABLE task and DISABLED event for MODE = Nrf_1Mbit and MODE = Ble_1Mbit	6		6	µs
t_RXEN,BLE,1M	Time between the RXEN task and READY event after channel FREQUENCY configured (1 Mbps BLE)	140		140	µs
t_{RXEN,FAST,BLE,1M}	Time between the RXEN task and READY event after channel FREQUENCY configured (1 Mbps BLE with fast ramp-up)	40		40	µs
t_RXDIS,BLE,1M	When in RX, delay between DISABLE task and DISABLED event for MODE = Nrf_1Mbit and MODE = Ble_1Mbit	0		0	µs
t_TXDIS,BLE,2M	When in TX, delay between DISABLE task and DISABLED event for MODE = Nrf_2Mbit and MODE = Ble_2Mbit	4		4	µs
t_RXDIS,BLE,2M	When in RX, delay between DISABLE task and DISABLED event for MODE = Nrf_2Mbit and MODE = Ble_2Mbit	0		0	µs
t_{TXEN,IEEE 802.15.4}	Time between TXEN task and READY event after channel FREQUENCY configured (IEEE 802.15.4 mode)	130		130	µs
t_{TXEN,FAST,IEEE 802.15.4}	Time between TXEN task and READY event after channel FREQUENCY configured (IEEE 802.15.4 mode with fast ramp-up)	40		40	µs
t_{TXDIS,IEEE 802.15.4}	When in TX, delay between DISABLE task and DISABLED event (IEEE 802.15.4 mode)	21		21	µs
t_{RXEN,IEEE 802.15.4}	Time between the RXEN task and READY event after channel FREQUENCY configured (IEEE 802.15.4 mode)	130		130	µs
t_{RXEN,FAST,IEEE 802.15.4}	Time between the RXEN task and READY event after channel FREQUENCY configured (IEEE 802.15.4 mode with fast ramp-up)	40		40	µs
t_{RXDIS,IEEE 802.15.4}	When in RX, delay between DISABLE task and DISABLED event (IEEE 802.15.4 mode)	0.5		0.5	µs
t_{RX-to-TX turnaround}	Maximum TX-to-RX or RX-to-TX turnaround time in IEEE 802.15.4 mode		40		µs

Received signal strength indicator (RSSI) specifications

Symbol	Description	Typ.	Units
RSSI_ACC	RSSI accuracy ⁵	±2	dB
RSSI_RESOLUTION	RSSI resolution	1	dB
RSSI_PERIOD	RSSI sampling time from RSSI_START task	0.25	µs
RSSI_SETTLE	RSSI settling time after signal level change	15	µs

Jitter

Symbol	Description				Min.	Typ.	Max.	Units
t_{DISABLEDJITTER}	Jitter on DISABLED event relative to END event when shortcut between END and DISABLE is enabled					0.25		µs
t_READYJITTER	Jitter on READY event relative to TXEN and RXEN task					0.25		µs

IEEE 802.15.4 mode energy detection constants

Symbol	Description				Min.	Typ.	Max.	Units
ED_RSSISCALE	Scaling value when converting between hardware-reported value and dBm					5
ED_RSSIOFFS	Offset value when converting between hardware-reported value and dBm					-93